參數(shù)資料
型號(hào)： AD9737A-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 47/64頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9737A
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9737A/AD9739A
Rev. | Page 51 of 64
After the controller is enabled during the initial SPI boot process
(see Table 29), the controller enters a search mode where it
seeks to find the closest rising edge of the DCI clock (relative to
a delayed version of an internal fDAC/4 clock) by simultaneously
adjusting the delays in the clocks used to register the DCI and
data inputs. A state machine searches above and below the
initial DCI_DEL value. The state machine first searches for the
first rising edge above the DCI_DEL and then searches for the
first rising edge below the DCI_DEL value. The state machine
selects the closest rising edge and then enters track mode. It is
recommended that the default midpoint delay setting (that is,
Decimal 167) for the DCI_DEL and SMP_DEL bits be kept to
ensure that the selected edge remains closest to the delay line
midpoint, thus providing the greatest range for tracking timing
variations and preventing the controller from falling out of lock.
The adjustable delay span for these internal clocks (that is, DCI and
sample delay) is nominally 4 ns. The 10-bit delay value is user
programmable from the decimal equivalent code (0 to 384)
with approximately 12 ps/LSB resolution via the DCI_DEL
(Register 0x13 and Register 0x14)and SMP_DEL registers
(Register 0x11 and Register 0x12). When the controller is enabled,
it overwrites these registers with the delay value it converges
upon. The minimum difference between this delay value and
the minimum/maximum values (that is, 0 and 384) represents
the guard band for tracking. Therefore, if the controller initially
converges upon a DCI_DEL and SMP_DEL value between 80
and 3044, the controller has a guard band of at least 80 code
(approximately 1 ns) to track phase variations between the
clock domains.
On initialization of the AD9737A/AD9739A, a certain period of
time is required for the data receiver controller to establish a lock
of the DCI clock signal. Note that, due to its dependency on the
Mu controller, the data receiver controller should be enabled
only after the Mu controllers have been enabled and established
lock. All of the internal controllers operate at a submultiple of
the DAC update rate. The number of fDAC clock cycles required
to lock onto the DCI clock is typically 70 k clock cycles but can
be up to 135 k clock cycles. During the SPI initialization process,
the user has the option of polling Register 0x21 (Bit 0, Bit 1, and
Bit 3) to determine if the data receiver controller is locked, has
lost lock, or has entered into track mode before completing the
boot sequence. Alternatively, the appropriate IRQ bit (Register 0x03
and Register 0x04) can be enabled such that an IRQ output signal
is generated upon the controller establishing lock.
The data receiver controller can also be configured to generate
an interrupt request (IRQ) upon losing lock. Losing lock can be
caused by disruption of the main DAC clock input or loss of a
power supply rail. To service the interrupt, the host can poll the
RCVR_LCK bit (Bit 0, Recister 0x21) to determine the current
state of the controller. If this bit is cleared, the search/track
procedure can be restarted by setting the RCVR_LOOP_ON bit
(Bit 1) in Register 0x10. After waiting the required lock time, the
host can poll the RCVR_LCK bit to see if it has been set. Before
leaving the interrupt routine, the RCVR_FLG_RST bit (Bit 2,
Register 0x10) should be reset by writing a high followed by a
low.
LVDS Driver and Receiver Input
The AD9737A/AD9739A feature an LVDS-compatible driver
and receivers. The LVDS driver output used for the DCO signal
includes an equivalent 200 Ω source resistor that limits its nominal
output voltage swing to ±200 mV when driving a 100 Ω load.
The DCO output driver can be powered down via Register 0x01,
Bit 5. An equivalent circuit is shown in Figure 162.
DCO_N
VSS
VDD33
DCO_P
V+
V–
100
VCM
100
ESD
09616-
082
Figure 162. Equivalent LVDS Output
VSS
VDD33
DCI_P
DBx[13:0]P
DCI_N
DBx[13:0]N
100
ESD
09616-
083
Figure 163. AD9739A Equivalent LVDS Input
C
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9739 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter
AD9739A 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter
AD9739ABBC 制造商:Analog Devices 功能描述:14 BIT 2.5 GSPS DAC A REVISION - Trays
AD9739ABBCRL 制造商:Analog Devices 功能描述:14 BIT 2.5 GSPS DAC A REVISION - Tape and Reel
AD9739ABBCZ 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14 Bit 2.5 GSPS DAC A Revision RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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