VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOU" />
參數(shù)資料
型號(hào)： AD9737A-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 62/64頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9737A
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9737A/AD9739A
Rev.
| Page 7 of 64
AC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS, unless otherwise noted.
Table 4.
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
DAC Clock Rate
1600
2500
1600
2500
MSPS
Adjusted DAC Update Rate1
1600
2500
1600
2500
MSPS
Output Settling Time to 0.1%
13
ns
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fOUT = 100 MHz
70
dBc
fOUT = 350 MHz
65
dBc
fOUT = 550 MHz
58
dBc
fOUT = 950 MHz
55
dBc
TWO-TONE INTERMODULATION DISTORTION (IMD),
fOUT2 = fOUT1 + 1.25 MHz
fOUT = 100 MHz
94
dBc
fOUT = 350 MHz
78
dBc
fOUT = 550 MHz
72
dBc
fOUT = 950 MHz
68
dBc
NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE
fOUT = 100 MHz
162
167
dBm/Hz
fOUT = 350 MHz
162
166
dBm/Hz
fOUT = 550 MHz
161
164
dBm/Hz
fOUT = 850 MHz
161
163
dBm/Hz
WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE
ADJACENT CHANNEL
fDAC = 2457.6 MSPS, fOUT = 350 MHz
80/81
80/80
dBc
fDAC = 2457.6 MSPS, fOUT = 950 MHz
75/75
78/79
dBc
fDAC = 2457.6 MSPS, fOUT = 1700 MHz (Mix-Mode)
69/71
74/74
dBc
fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix-Mode)
66/67
69/72
dBc
1 Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor
is 1. Thus, with fDAC = 2500 MSPS, fDAC, adjusted, = 2500 MSPS.
C
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