Table 3
參數(shù)資料
型號(hào)： AD9737A-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 56/64頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9737A
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9737A/AD9739A
Data Sheet
Rev. | Page 6 of 64
SERIAL PORT SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.
Table 3.
Parameter
Min
Typ
Max
Unit
WRITE OPERATION (See Figure 154)
SCLK Clock Rate, fSCLK, 1/tSCLK
20
MHz
SCLK Clock High, tHIGH
18
ns
SCLK Clock Low, tLOW
18
ns
SDIO to SCLK Setup Time, tDS
2
ns
SCLK to SDIO Hold Time, tDH
1
ns
CS to SCLK Setup Time, tS
3
ns
SCLK to CS Hold Time, tH
2
ns
SCLK Clock Rate, fSCLK, 1/tSCLK
20
MHz
SCLK Clock High, tHIGH
18
ns
SCLK Clock Low, tLOW
18
ns
SDIO to SCLK Setup Time, tDS
2
ns
SCLK to SDIO Hold Time, tDH
1
ns
CS to SCLK Setup Time, tS
3
ns
SCLK to SDIO (or SDO) Data Valid Time, tDV
15
ns
CS to SDIO (or SDO) Output Valid to High-Z, tEZ
2
ns
INPUTS (SDI, SDIO, SCLK, CS)
Voltage in High, VIH
2.0
3.3
V
Voltage in Low, VIL
0
0.8
V
Current in High, IIH
10
+10
A
Current in Low, IIL
10
+10
A
OUTPUT (SDIO)
Voltage Out High, VOH
2.4
3.5
V
Voltage Out Low, VOL
0
0.4
V
Current Out High, IOH
4
mA
Current Out Low, IOL
4
mA
C
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