參數(shù)資料
型號(hào)： AD9787BSVZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/64頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 800MSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
系列： TxDAC®
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 800M
AD9785/AD9787/AD9788
Rev. A | Page 33 of 64
INPUT DATA PORTS
The AD9785/AD9787/AD9788 can operate in two data input
modes: dual-port mode and single-port mode. In the default
dual-port mode (single-port mode = 0), each DAC receives data
from a dedicated input port. In single-port mode (single-port
mode = 1), both DACs receive data from Port 1. In single-port
mode, DAC 1 and DAC 2 data is interleaved and the TXENABLE
input is used to steer data to the intended DAC. In dual-port
mode, the TXENABLE input is used to power down the digital
datapath.
In dual-port mode, the data must be delivered at the input data
rate. In single-port mode, data must be delivered at twice the
input data rate of each DAC. Because the data inputs function up
to a maximum of 300 MSPS, it is only practical to operate with
input data rates up to 150 MHz per DAC in single-port mode.
In both dual-port and single-port modes, a data clock output
(DATACLK) signal is available as a fixed-time base with which
to drive data from an FPGA (field programmable gate array) or
from another data source. This output signal operates at the
input data rate. The DATACLK pin can operate as either an
input or an output.
SINGLE-PORT MODE
In single-port mode, data for both DACs is received on the
Port 1 input bus (P1D[15:0]). I and Q data samples are inter-
leaved and are latched on the rising edges of DATACLK.
Accompanying the data is the TXENABLE (Pin 39) input
signal, which steers incoming data to its respective DAC. When
TXENABLE is high, the corresponding data-word is sent to the
I DAC and, when TXENABLE is low, the corresponding data is
sent to the Q DAC. The timing of the digital interface in
interleaved mode is shown in Figure 48.
The Q first bit (Register 0x01, Bit 1) controls the pairing
order of the input data. With the Q first bit set to the default
of 0, the I/Q pairing sent to the DACs is the two input data-
words corresponding to TXENABLE low followed by
TXENABLE high.
With the Q first bit set to 1, the I/Q pairing sent to the DACs is
the two input data-words corresponding to TXENABLE high
followed by TXENABLE low. Note that with Q first set, the
I data still corresponds to the TXENABLE high word and the
Q data corresponds to the TXENABLE low word and only the
pairing order changes.
DUAL-PORT MODE
In dual-port mode, data for each DAC is received on the
respective input bus (P1D[15:0] or P2D[15:0]). I and Q data
arrive simultaneously and are sampled on the rising edge of an
internal sampling clock (SMP_CLK) that is synchronous with
DATACLK. In dual-port mode, driving the TXENABLE input
low powers down the digital datapath. TXENABLE should be
held high during normal data transmission.
INPUT DATA REFERENCED TO DATACLK
The simplest method of interfacing to the AD9785/AD9787/
AD9788 is when the input data is referenced to the DATACLK
output. The DATACLK output is phase-locked (with some
offset) to the internal clock that is used to latch the input data.
Therefore, if the setup and hold times of the input data with
respect to DATACLK are met, the interface timing latches in the
data correctly.
Table 25 shows the setup and hold time requirements for the
input data over the operating temperature range of the device.
Table 25 also shows the data valid window (DVW). The data
valid window is the sum of the setup and hold times of the
interface. This is the minimum amount of time valid data must
be presented to the device in order to ensure proper sampling.
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