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參數(shù)資料
| 型號： | AD9787BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 46 of 64
Table 33 lists the register settings required to enable the PN
code mode synchronization feature.
Table 33. Register Settings for Enabling PN Code Mode
Register
Bit
Parameter
Value
0x01
[13]
PN code sync enable
1
[12]
Sync mode select
1
[11]
Pulse sync enable
0
0x03
[31:27]
Correlate Threshold
[4:0]
10000
[26]
SYNC_I enable
1
[25]
SYNC_O enable
0 (slave devices)
1 (master device)
[10]
Set high
1
To verify that the devices have successfully synchronized, read
back the sync lock status bit on all devices (Register 0x09,
Bit 10). The sync lock status bit should read back as 1 on all
devices. Next, read back the sync lock lost status bit on all
devices (Register 0x09, Bit 11). The sync lock lost status bit
should read back as 0 on all devices. To clear the sync lock lost
status bit, set the clear lock indicator bit to 1, followed by a 0
(Register 0x09, Bit 12).
Because the SYNC_O signal generated by the master is spread
over many bits, this method of synchronization is very robust.
Any individual bits that may become corrupted or somehow
misread by the slave device usually have no effect on the
synchronization of the device. If the devices do not reliably
synchronize, there are several options for correcting the situation.
The SYNC_O Delay [4:0] value (Register 0x03, Bits [15:11]) on
the master device can be used to adjust the timing in 80 ps steps
effective across all devices. In addition, the SYNC_O polarity bit
(Register 0x03, Bit 9) on the master device can be set to provide
a delay of one half the DACCLK period. The SYNC_I Delay [4:0]
bits (Register 0x03, Bits [23:19]) can be used to adjust the
timing on a single slave device in 80 ps steps.
The Correlate Threshold [4:0] value (Register 0x03,
Bits [31:27]) indicates how closely the code of the received
SYNC_I signal is to the expected code. A high threshold
requires a closer match of the encoded signal to set the
sync lock status bit; a lower value reduces the matching
requirements to set the sync lock status bit.
Increasing the Correlate Threshold [4:0] value makes the part
more resistant to false synchronization locks but requires a
lower bit error rate on the SYNC_I input to maintain locked
status. Decreasing the Correlate Threshold [4:0] value makes
the part more susceptible to false synchronization locks, but
maintains a locked status in the face of a higher bit error rate
on the SYNC_I input (that is, it is more noise resistant). The
recommended value for Correlate Threshold [4:0] is the default
value of 16.
INTERRUPT REQUEST OPERATION
The IRQ pin (Pin 71) acts as an alert that the device has
experienced a timing error and that it should be queried (by
reading Register 0x09) to determine the exact fault condition.
The IRQ pin is an open-drain, active low output. The IRQ pin
should be pulled high external to the device. This pin may be
tied to the IRQ pins of other devices with open-drain outputs to
wire-OR these pins together.
There are two different error flags that can trigger an interrupt
request: a data timing error or a sync timing error. By default,
when either or both of these error flags are set, the IRQ pin is
active low. Either or both of these error flags can be masked to
prevent them from activating an interrupt on the IRQ pin.
The error flags are latched and remain active until the flag bits
are overwritten.
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