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參數(shù)資料
| 型號： | AD9787BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 37 of 64
Manual Timing Optimization Mode
When the device is operating in manual timing optimization
mode (Register 0x02, Bit 3 = 0), the device does not alter the
DATACLK Delay [4:0] value that is programmed by the user. By
default, the DATACLK delay enable is inactive. This bit must be
set high for the DATACLK Delay [4:0] value to be realized.
The delay (in absolute time) when programming the DATACLK
delay from 00000 to 11111 varies from about 700 ps to about
6.5 ns. Typical delays per increment over temperature are shown
Table 27. Data Delay Line Typical Delays over Temperature
Delay
40°C
+25°C
+85°C
Unit
Zero code delay (delay upon
enabling delay line)
630
700
740
ps
Average unit delay
175
190
210
ps
In manual mode, the error checking logic is activated and
generates an interrupt if a setup/hold violation is detected. One
error check operation is performed per device configuration.
Any change to the Data Timing Margin [3:0] or DATACLK
Delay [4:0] values triggers a new error check operation.
INPUT DATA RAM
The AD9785/AD9787/AD9788 feature on-chip RAM that can
be used as an alternative input data source to the input data pins.
The input data RAM is loaded through the SPI port. After the
input data is stored in memory, the device can be configured to
transmit the stored data instead of receiving data through the
input data pins. This can be a useful test mode for factory or
in-system testing.
The RAM is 64 words long and 32 bits wide. The 16 MSBs drive
the I datapath, and the 16 LSBs drive the Q datapath. The RAM
configuration is shown in Figure 54.
07
098-
060
64 WORDS
RA
M
I-SIDE
Q-SIDE
32 BITS
16 BITS
0x1D
Figure 54. Input Data RAM Configuration
The data can be written to the RAM in either LSB first or MSB
first format.
To write to the RAM in MSB first format, complete the
following steps:
1.
Set Bit 6 of Register 0x00 to 0.
2.
Apply an instruction byte of 0xEE followed by the data to
be stored.
After the instruction byte (a write to Register 0x1D) is received,
the device automatically generates the addresses required to write
the RAM, starting at the most significant address. The 32 rising
SCLK edges following the instruction byte write the first RAM
word. At this time, the internal address generator decrements
and the next 32 rising edges of SCLK write the second RAM
word. This cycle of decrementing the RAM address and writing
32-bit words continues until the last word is written. After the
64th word is written, the communication cycle is complete.
To write to the RAM in LSB first format, complete the following
steps:
1.
Set Bit 6 of Register 0x00 to 1.
2.
Apply an instruction byte of 0xEE followed by the data to
be stored.
All memory elements must be accessed to complete a commu-
nication cycle. Note that the RAM is not a dual-port memory
element; therefore, if an I/O operation is begun while the RAM
is being used to drive data into the signal processing path, the
I/O operation has priority.
To begin using the RAM as an internal data generator, set
Register 0x1E (test register) to a value of 0x00C000. After these
24 bits are written, the DAC starts to output the waveform
stored in memory.
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