參數(shù)資料
型號(hào)： AD9787BSVZRL
廠商： Analog Devices Inc
文件頁數(shù)： 36/64頁
文件大小： 0K
描述： IC DAC 14BIT 800MSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
系列： TxDAC®
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 800M
AD9785/AD9787/AD9788
Rev. A | Page 41 of 64
Table 31. Inverse Sinc Filter
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(9)
+2
H(2)
H(8)
4
H(3)
H(7)
+10
H(4)
H(6)
35
H(5)
–
+401
The inverse sinc filter is disabled by default. It can be enabled by
setting the inverse sinc enable bit (Bit 9) in Register 0x01.
DIGITAL AMPLITUDE AND OFFSET CONTROL
The gain of the I datapath and the Q datapath can be independ-
ently scaled by adjusting the I DAC Amplitude Scale Factor [8:0]
or Q DAC Amplitude Scale Factor [8:0] value in Register 0x0C.
These values control the input to a digital multiplier. The value
of the scale factor ranges from 0 to 3.9921875 and can be
calculated as follows:
128
]
0
:
8
[
Factor
Scale
Value
Factor
Scale
The digital scale factor can be used to compensate for amplitude
imbalance between the I and Q channels or to provide equal
gain scaling to both channels for output level adjustment. Note
that when the gain is set to 1.0 (scale factor = 0x80), the gain
block is bypassed. When bypassed, the gain block has a different
delay from when it is used. Therefore, to maintain matched
latency in each path, both gain blocks should be set to exactly
1.0, or neither path should be set to exactly 1.0. Failing to
maintain matched latencies in the I and Q paths creates a phase
imbalance in quadrature signals, which results in poor sideband
suppression of upconverted signals.
The dc value of the I datapath and the Q datapath can also be
independently controlled. This is accomplished by adjusting
the I DAC Offset [15:0] and Q DAC Offset [15:0] values in
Register 0x0D. These values are added directly to the datapath
values. Care should be taken not to overrange the transmitted
values.
Figure 59 shows how the DAC offset current varies as a function
of the I DAC Offset [15:0] and Q DAC Offset [15:0] values. With
the digital inputs fixed at midscale (0x0000, twos complement
data format), the figure shows the nominal IOUTx_P and IOUTx_N
currents as the DAC offset value is swept from 0 to 65535.
Because IOUTx_P and IOUTx_N are complementary current outputs,
the sum of IOUTx_P and IOUTx_N is always 20 mA.
0x0000
0x4000
0x8000
0xC000
0xFFFF
5
10
15
20
5
10
15
20
0
DAC OFFSET VALUE
I O
U
T
x_N
(m
A
)
I O
U
T
x_P
(m
A
)
07
09
8-
10
8
Figure 59. DAC Output Currents vs. DAC Offset Value
The offset currents generated by the DAC offset parameter
increase from 0 mA to 10 mA as the offset is swept from 0 to
0x7FFF. The offset currents increase from 10 mA to 0 mA as
the offset is swept from 0x8000 to 0xFFFF.
DIGITAL PHASE CORRECTION
The purpose of the phase correction block is to enable compens-
ation of the phase imbalance of the analog quadrature modulator
following the DAC. If the quadrature modulator has a phase
imbalance, the unwanted sideband appears with significant
energy. Adjusting the phase correction word can optimize image
rejection in single sideband radios.
Ordinarily the I and Q channels have an angle of precisely 90°
between them. The Phase Correction Word [9:0] (Register 0x0B)
is used to change the angle between the I and Q channels. When
the Phase Correction Word [9:0] is set to 1000000000b, the
Q DAC output moves approximately 14° away from the I DAC
output, creating an angle of 104° between the channels. When
the Phase Correction Word [9:0] is set to 0111111111b, the
Q DAC output moves approximately 14° towards the I DAC
output, creating an angle of 76° between the channels. Based on
these two endpoints, the resolution of the phase compensation
register is approximately 28°/1024 or 0.027° per code.
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