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參數(shù)資料
| 型號： | AD9787BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 49 of 64
Configuring the PLL Band Select Value
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.0 GHz covered in 63 overlapping frequency bands
as shown in Table 35. For any desired VCO output frequency,
there are multiple valid PLL band select values. Note that the
data shown in Table 35 is for a typical device. Device-to-device
variations can shift the actual VCO output frequency range by
30 MHz to 40 MHz. Also, the VCO output frequency varies as
a function of temperature. Therefore, it is required that the
optimal PLL band select value be determined for each
individual device at the particular operating temperature.
The device has an automatic PLL band select feature on chip.
When enabled, the device determines the optimal PLL band
setting for the device at the given temperature. This setting holds
for a ±60°C temperature swing in ambient temperature. If the
device operates in an environment that experiences a larger
temperature swing, an offset should be applied to the automat-
ically selected PLL band. The following procedure outlines a
method for setting the PLL band select value for a device
operating at a particular temperature that holds for a change in
ambient temperature over the total 40°C to +85°C operating
range of the device without further user intervention. (Note that
REFCLK must be applied to the device during this procedure.)
Configuring PLL Band Select with Temperature Sensing
The values of N1 (Register 0x04, Bits [14:13]) and N2
(Register 0x04, Bits [12:11]) should be programmed along
with the PLL settings shown in Table 34.
1.
Set the PLL Band Select [5:0] value (Register 0x04,
Bits [7:2]) to 63 to enable PLL auto mode.
2.
Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x09, Bit 3) to go high. This should occur
within 5 ms.
3.
Read back the 6-bit PLL band select value (Register 0x04,
Bits [7:2]).
4.
Based on the temperature when the PLL auto mode is
enabled, set the PLL band indicated in Table 36 or Table 37
by rewriting the readback values into the PLL Band Select
[5:0] parameter (Register 0x04, Bits [7:2]).
Table 36. Setting Optimal PLL Band for Lower Range
(0 to 31) Bands
System Start-Up Temperature
Set PLL Band to
40°C to 10°C
Readback Band + 2
10°C to +15°C
Readback Band + 1
15°C to 55°C
Readback Band
55°C to 85°C
Readback Band 1
Table 37. Setting Optimal PLL Band for Higher Range
(32 to 62) Bands
System Start-Up Temperature
Set PLL Band to
40°C to 30°C
Readback Band + 3
30°C to 10°C
Readback Band + 2
10°C to +15°C
Readback Band + 1
15°C to 55°C
Readback Band
55°C to 85°C
Readback Band 1
Known Temperature Calibration with Memory
The procedure in the Configuring PLL Band Select with
Temperature Sensing section requires temperature sensing
upon start-up or reset of the device to choose the optimal PLL
band select value to hold over the entire operating temperature
range. If temperature sensing is not available in the system,
another option is to use the automatic PLL band select to
determine the optimal setting for the device when the device is
in a factory environment where the temperature is known. The
optimal band can then be stored in nonvolatile memory.
Whenever the system is powered up or restarted, the optimal
value can be loaded back into the device.
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