參數(shù)資料
型號(hào)： AD9912A/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 5/40頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9912
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9912
主要屬性： 14 位數(shù)模轉(zhuǎn)換器，48 位調(diào)節(jié)字寬
次要屬性： 1GHz 圖形用戶界面
已供物品： 板
AD9912
Rev. F | Page 13 of 40
06
76
3-
01
5
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–100
–110
–120
–130
–140
–150
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
800MHz
600MHz
RMS JITTER (100Hz TO 100MHz):
600MHz:
800MHz:
585fs
406fs
Figure 15. Absolute Phase Noise Using HSTL Driver,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed),
HSTL Output Doubler Enabled
06
76
3-
0
16
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–110
–120
–130
–140
–150
–160
P
HAS
E
NO
IS
E
(
d
Bc/
H
z
)
150MHz
50MHz
10MHz
RMS JITTER (100Hz TO 20MHz):
150MHz:
50MHz:
308fs
737fs
Figure 16. Absolute Phase Noise Using CMOS Driver at 3.3 V,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
DDS Run at 200 MSPS for 10 MHz Plot
06
76
3-
01
7
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–110
–120
–130
–140
–150
–160
P
HAS
E
NO
IS
E
(d
Bc/
H
z
)
50MHz
10MHz
RMS JITTER (100Hz TO 20MHz):
50MHz:
790fs
Figure 17. Absolute Phase Noise Using CMOS Driver at 1.8 V,
SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)
06
76
3-
0
18
250
375
500
625
750
875
1000
SYSTEM CLOCK FREQUENCY (MHz)
800
700
600
500
400
300
200
100
0
P
O
W
E
R
DI
S
IP
AT
IO
N
(m
W
)
TOTAL
3.3V
1.8V
Figure 18. Power Dissipation vs. System Clock Frequency
(SYSCLK PLL Bypassed), fOUT = fSYSCLK/5, HSTL Driver On, CMOS Driver On,
SpurKiller Off
06
76
3-
0
19
0
100
200
300
400
OUTPUT FREQUENCY (MHz)
800
700
600
500
400
300
200
100
0
P
O
W
E
R
DI
S
IP
AT
IO
N
(m
W
)
TOTAL
3.3V
1.8V
Figure 19. Power Dissipation vs. Output Frequency
SYSCLK = 1 GHz (SYSCLK PLL Bypassed), HSTL Driver On,
CMOS Driver On, SpurKiller Off
06
76
3-
0
20
0
100
200
300
400
500
FREQUENCY (MHz)
–20
–30
–40
10
0
–10
–50
–60
–70
–80
–90
–100
SI
G
N
A
L
PO
W
ER
(d
B
m
)
CARRIER:
SFDR W/O SPURKILLER:
SFDR WITH SPURKILLER:
FREQUENCY SPAN:
RESOLUTION BW:
VIDEO BW:
399MHz
–63.7dBc
–69.3dBc
500MHz
3kHz
30kHz
THESE TWO SPURS
ELIMINATED WITH
SPURKILLER
Figure 20. SFDR Comparison With and Without SpurKiller,
SYSCLK = 1 GHz, fOUT = 400 MHz
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