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| 型號(hào)： | AD9974BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 托盤 |
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AD9974
Rev. A | Page 31 of 52
SHA Mode—Differential Input Configuration
This configuration uses a differential input sample/hold
amplifier (SHA) (see Figure 43).
IMAGE
SENSOR
SHA/
CDS
CCDINM
CCDINP
AD9974
05
95
5-
04
3
Figure 43. SHA Mode—Differential Input Configuration
In this configuration, a signal is applied to the CCDINP input
and, simultaneously, an inverse signal is applied to the CCDINM
input. Sampling occurs on both signals at the same time. This
creates the differential output for amplification and the ADC
(N + 1) SIGNAL SAMPLE
(N) SIGNAL SAMPLE
INPUT_POS
INPUT_NEG
PEAK SIGNAL
LEVEL (VFS)
BLACK SIGNAL LEVEL (VBLK)
MINIMUM SIGNAL LEVEL (VMIN)
GND
05
95
5-
04
4
Figure 44. SHA Mode—Differential Input Signal
Table 18. SHA Mode—Differential Voltage Levels
Signal Level
Symbol
Min (mV)
Typ (mV)
Max (mV)
Black
VBLK
0
Saturation
VFS
1000
VDD 300
1400
Minimum
VMIN
0
1800
SHA Mode—DC-Coupled, Single–Ended Input
The SHA mode can also be used in a single-ended fashion, with
the signal from the image sensor applied to the CDS/SHA using
a single input, CCDINP. This is similar to the differential configu-
ration, except in this case, the CCDINM line is held at a constant
dc voltage, establishing a reference level that matches the image
sensor reference voltage (see Figure 45).
IMAGE
SENSOR
SHA/
CDS
CCDINM
CCDINP
AD9974
NOTES
1. DC VOLTAGE ABOVE GROUND MAYBE USED TO
MATCH THE SENSOR REFERENCE LEVEL.
059
55
-04
5
Figure 45. SHA Mode—Single–Ended Input Configuration, DC-Coupled
constant dc voltage set at a level above ground potential. The
sensor signal is applied to the other input, and samples are taken
at the signal minimum and at a point of signal maximum. The
resulting differential signal is the difference between the signal
and the reference voltage.
(N + 1) SIGNAL SAMPLE
(N) SIGNAL SAMPLE
INPUT_POS
INPUT_NEG
PEAK SIGNAL
LEVEL (VFS)
BLACK SIGNAL LEVEL (VBLK)
MINIMUM SIGNAL LEVEL (VMIN)
GND
0
59
55
-04
6
Figure 46. SHA Mode—Single–Ended Input Signal (DC-Coupled)
Table 19. SHA Mode—Single-Ended Input Voltages
Signal Level
Symbol
Min (mV)
Typ (mV)
Max (mV)
Black
VBLK
0
Saturation
VFS
1000
1400
Minimum
VMIN
0
CDS Timing Control
The timing shown in Figure 21 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and data level of the CCD signal, respectively. The
placement of the SHP and SHD sampling edges is determined by
the setting of the SHPLOC and SHDLOC register located at
Address 0x36. Placement of these two clock signals is critical in
achieving the best performance from the CCD.
SHA Timing Control
When SHA mode is selected, only the SHPLOC setting is used
to sample the input signal, but the SHDLOC signal should still
be programmed to an edge setting of SHPLOC + 32.
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| AD9974BBCZRL | 功能描述:IC CCDSP DUAL 14BIT 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9975 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTEB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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