X = A = B, AVDD_X = 1.8 V, fCLI = 65" />
參數(shù)資料
型號(hào): AD9974BBCZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 49/52頁(yè)
文件大小: 0K
描述: IC CCDSP DUAL 14BIT 100-CSPBGA
標(biāo)準(zhǔn)包裝: 1
類型: CCD 信號(hào)處理器,14 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 55mA
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(9x9)
包裝: 托盤(pán)
AD9974
Rev. A | Page 6 of 52
ANALOG SPECIFICATIONS
X = A = B, AVDD_X = 1.8 V, fCLI = 65 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Allowable CCD Reset Transient
0.5
0.8
V
CDS Gain Accuracy
3 dB CDS Gain
3.3
2.8
2.3
0 dB CDS Gain (Default)
0.7
0.2
+0.3
3 dB CDS Gain
2.3
2.8
3.3
6 dB CDS Gain
4.9
5.4
5.9
Maximum Input Voltage
VGA gain = 5.6 dB (Code 15, default value)
3 dB CDS Gain
1.4
V p-p
0 dB CDS Gain (Default)
1.0
V p-p
3 dB CDS Gain
0.7
V p-p
6 dB CDS Gain
0.5
V p-p
Allowable OB Pixel Amplitude
0 dB CDS Gain (Default)
100
+200
mV
6 dB CDS Gain
50
+100
mV
VARIABLE GAIN AMPLIFIER (VGA_X)
Gain Control Resolution
1024
Steps
Gain Monotonicity
Guaranteed
Low Gain Setting (VGA Code 15, Default)
6
dB
Maximum Gain Setting (VGA Code 1023)
42
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
1024
Steps
Minimum Clamp Level (Code 0)
0
LSB
Measured at ADC output
Maximum Clamp Level (Code 1023)
1023
LSB
Measured at ADC output
ADC (CHN_A and CHN_B)
Resolution
14
Bits
Differential Nonlinearity (DNL)
1.0
±0.5
+1.2
LSB
No Missing Codes
Guaranteed
Integral Nonlinearity (INL)
5
15
LSB
Full-Scale Input Voltage
2.0
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT_X)
1.4
V
Reference Bottom Voltage (REFB_X)
0.4
V
SYSTEM PERFORMANCE
Specifications include entire signal chain
VGA Gain Accuracy
0 dB CDS gain (default)
Low Gain (Code 15)
5.1
5.6
6.1
dB
Gain = (0.0359 × code) + 5.1 dB
Maximum Gain (Code 1023)
41.3
41.8
42.3
dB
Peak Nonlinearity, 500 mV Input Signal
0.1
0.4
%
12 dB total gain applied
Total Output Noise
2
LSB rms
AC-grounded input, 6 dB gain applied
Power Supply Rejection (PSR)
48
dB
Measured with step change on supply
1 Input signal characteristics are defined as shown in
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