參數(shù)資料
型號: ADF4208BRUZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 13/24頁
文件大?。?/td> 0K
描述: IC PLL FREQ SYNTHESIZER 20TSSOP
標準包裝: 2,500
類型: 時鐘/頻率合成器,RF
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 3:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 2GHz
除法器/乘法器: 無/無
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
ADF4206/ADF4208
Rev. A | Page 20 of 24
APPLICATIONS SECTION
LOCAL OSCILLATOR FOR GSM HANDSET
RECEIVER
Figure 33 shows the ADF4208 used in a classic superheterodyne
receiver to provide the required local oscillators (LOs).
In this circuit, the reference input signal is applied to the circuit
at OSCIN and is generated by a 10 MHz crystal oscillator. This is
a low cost solution. For better performance over temperature, a
TCXO (temperature controlled crystal oscillator) can be used
instead.
To have a channel spacing of 200 kHz (the GSM standard),
the reference input must be divided by 50 using the on-chip
reference counter.
The RF output frequency range is 1050 MHz to 1086 MHz. Loop
filter component values are chosen so that the loop bandwidth is
20 kHz. The synthesizer is set up for a charge pump current of
4.375 mA and the VCO sensitivity is 15.6 MHz/V.
The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.
OSCOUT
MUXOUT
ADF4208
VP2
VDD2 VDD1VP1
CPRF1
RF2IN
RF1IN
OSCIN
CLK
DATA
LE
DG
ND
RF
1
DG
N
D
RF
2
AG
ND
RF
1
AG
ND
RF
2
DECOUPLING CAPACITORS (22F/10pF) ON VDD, VP OF
THE ADF4208, AND ON VCC OF THE VCOs HAVE BEEN
OMITTED FROM THE DIAGRAM TO AID CLARITY.
VCO190-125T
VCC
CPRF2
VCC
S
P
I-
CO
M
P
AT
IBL
E
S
E
RI
AL
BUS
100pF
18
100pF
IFOUT
100pF
51
30pF
10MHz
18k
1.3nF
13nF
2.7k
620pF
3.3k
VP
VDD
VP
100pF
18
RFOUT
100pF 18
18
100pF
51
LOCK DETECT
30pF
VCO190-1068U
01
03
6-
0
35
Figure 32. GSM Handset Receiver Local Oscillator Using the ADF4208
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