V
參數(shù)資料
型號(hào)： ADF4208BRUZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 0K
描述： IC PLL FREQ SYNTHESIZER 20TSSOP
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 時(shí)鐘/頻率合成器，RF
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 3:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 2GHz
除法器/乘法器： 無(wú)/無(wú)
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
ADF4206/ADF4208
Rev. A | Page 4 of 24
Parameter
B Version1
Unit
Test Conditions/Comments
POWER SUPPLIES
VDD1
2.7/5.5
V min/V max
VDD2
VDD1
VP
VDD1/6.0
V min/V max
VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V
IDD (IDD1 + IDD2)6
ADF4206
14
mA max
9.5 mA typical at VDD = 3 V, TA = 25°C
ADF4208
21
mA max
14 mA typical at VDD = 3 V, TA = 25°C
IDD1
ADF4206
8
mA max
5.5 mA typical at VDD = 3 V, TA = 25°C
ADF4208
14
mA max
9 mA typical at VDD = 3 V, TA = 25°C
IDD2
ADF4206
7.5
mA max
5 mA typical at VDD = 3 V, TA = 25°C
ADF4208
9
mA max
5.5 mA typical at VDD = 3 V, TA = 25°C
IP (IP1 + IP2)
1
mA max
TA = 25°C
Low Power Sleep Mode
0.5
μA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(RF1)7
ADF4206
213
dBc/Hz typ
ADF4208
217
dBc/Hz typ
Phase Noise Performance8
@ VCO output
ADF4206 (RF1, RF2)
92
dBc/Hz typ
@ 540 MHz output, 200 kHz at PFD
ADF4208 (RF1)
85
dBc/Hz typ
@ 1750 MHz output, 200 kHz at PFD
ADF4208 (RF1)
91
dBc/Hz typ
@ 900 MHz output, 200 kHz at PFD
Spurious Signals
RF1, RF2 (20 kHz Loop B/W)
80/84
dB typ
@ 200 kHz/400 kHz offsets and
200 kHz PFD
1 Operating temperature range for B version: 40°C to +85°C.
2 The B chip specifications are given as typical values.
3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4 AC coupling ensures AVDD/2 bias. VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels.
5 Guaranteed by design. Sample tested to ensure compliance.
6 Typical values apply for VDD = 3 V; P = 32; RF1IN1/RF2IN2 for ADF4206 = 540 MHz; RF1IN1/RF2IN2 for ADF4208 = 900 MHz.
7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT 10 log FPFD 20 log N.
8 The phase noise is measured at 1 kHz, unless otherwise noted. The phase noise is measured with the EVAL-ADF4206EB or the EVAL-ADF4208EB evaluation board and
the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
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