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參數(shù)資料
| 型號(hào)： | ADF4208BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 2GHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
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ADF4206/ADF4208
Rev. A | Page 12 of 24
CONTROL
MUX
DVDD
MUXOUT
DGND
RF2 ANALOG LOCK DETECT
RF2 R COUNTER OUTPUT
RF2 N COUNTER OUTPUT
RF2/RF1 ANALOG LOCK DETECT
RF1 R COUNTER OUTPUT
RF1 N COUNTER OUTPUT
RF1 ANALOG LOCK DETECT
01
03
6-
0
26
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 25 is a simplified
schematic.
DELAY
ELEMENT
U3
CLR2
Q2
D2
U2
CLR1
Q1
D1
CHARGE
PUMP
DOWN
UP
HI
U1
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
VP
01
036
-02
5
Figure 26. MUXOUT Circuit
LOCK DETECT
MUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect is operated with an
external pull-up resistor of 10 kΩ nominal. When lock is
detected, it is high with narrow, low going pulses.
INPUT SHIFT REGISTER
The functional block diagram for the ADF420x family is shown
in Figure 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and a 17-bit N counter, comprising a 6-bit
A counter and an 11-bit B counter. Data is clocked into the
22-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs (DB1, DB0) as
shown in the timing diagram of Figure 2.
Table 5 is the truth table for these bits.
Table 5. C2, C1 Truth Table
Figure 25. PFD Simplified Schematic and Timing (In Lock)
The PFD includes a delay element that sets the width of the
antibacklash phase. The typical value for this in the ADF420x
family is 3 ns. The pulse ensures that there is no dead zone in
the PFD transfer function and minimizes phase noise and
reference spurs.
Control Bits
C2
C1
Data Latch
0
RF2 R counter
0
1
RF2 AB counter (and prescaler select)
1
0
RF1 R counter
1
RF1 AB counter (and prescaler select)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4206 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11, and P12. See Figure 28
and Figure 30. Figure 26 shows the MUXOUT circuit in block
diagram form.
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