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參數(shù)資料
| 型號： | ADF4360-9BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER W/ADJ VCO 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADF4360-9
Rev. C | Page 19 of 24
N COUNTER LATCH
Figure 24 shows the input data format for programming the
N counter latch.
5-Bit Divider
A5 to A1 program the output divider. The divide range is 2 (00010)
to 31 (11111). If unused, this divider should be set to 0. The output
or the output divided by 2 is available at the DIVOUT pin.
Reserved Bits
DB23, DB22, and DB7 are spare bits and are designated as
reserved. They should be programmed to 0.
B Counter Latch
B13 to B1 program the B counter. The divide range is 3
(00 … 0011) to 8191 (11 … 111).
Overall Divide Range
The overall VCO feedback divide range is defined by B.
CP Gain
DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When it is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is
used. This bit can also be programmed through DB10 of the
control latch. The bit always reflects the latest value written to it,
whether this is through the control latch or the N counter latch.
R COUNTER LATCH
With (C2, C1) = (0, 1), the R counter latch is programmed.
Figure 25 shows the input data format for programming the
R counter latch.
R Counter
R1 to R14 set the counter divide ratio. The divide range is
1 (00 … 001) to 16,383 (111 … 111).
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
Lock Detect Precision
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with <15 ns phase error for entering the locked
state. With LDP at 1, five cycles are taken; with LDP at 0, three
cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs, as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be
programmed by the user.
Band Select Clock
These bits (DB20 and DB21) set a divider for the band select
logic clock input. The output of the R counter is, by default, the
value used to clock the band select logic; if this value is too high
(>1 MHz), a divider can be switched on to divide the R counter
output to a smaller value (see Figure 25). A value of 8 is
recommended.
Reserved Bits
DB23 to DB22 are spare bits that are designated as reserved.
They should be programmed to 0.
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| ADF4360-9BCPZRL7 | 功能描述:IC SYNTHESIZER W/ADJ VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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| ADF4602-1XCPZ | 制造商:Analog Devices 功能描述:SINGLE-CHIP, MULTIBAND 3G FEMTOCELL TRANSCEIVER - Rail/Tube |
| ADF4602-1XCPZ-RL | 制造商:Analog Devices 功能描述: |
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