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參數(shù)資料
| 型號： | ADF4360-9BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER W/ADJ VCO 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADF4360-9
Rev. C | Page 17 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-9 after
power-up is as follows:
1. R Counter Latch
2. Control Latch
3. N Counter Latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AVDD, DVDD, and VVCO pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-9 during initial power-up to settle.
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-9 may not achieve lock. If the
recommended interval is inserted, and the N counter latch is
programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the CN pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-9 VCO. The
recommended value of this capacitor is 10 F. Using this
value requires an interval of ≥15 ms between the latching in
of the control latch bits and latching in of the N counter latch
bits. If a shorter delay is required, the capacitor can be reduced.
A slight phase noise penalty is incurred by this change, which is
further explained in Table 6.
Table 6. CN Capacitance vs. Interval and Phase Noise
CN Value
Recommended Interval Between
Control Latch and N Counter Latch
Open-Loop Phase Noise @ 10 kHz Offset
L1 and L2 = 18.0 nH
L1 and L2 = 110.0 nH
L1 and L2 = 560.0 nH
10 F
≥15 ms
100 dBc/Hz
97 dBc/Hz
99 dBc/Hz
440 nF
≥600 s
99 dBc/Hz
96 dBc/Hz
98 dBc/Hz
CLK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
07139-
033
Figure 26. Power-Up Timing
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| ADF4360-9BCPZRL7 | 功能描述:IC SYNTHESIZER W/ADJ VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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