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參數(shù)資料
| 型號： | ADF4360-9BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER W/ADJ VCO 24LFCSP |
| 標準包裝： | 5,000 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADF4360-9
Rev. C | Page 11 of 24
shows a summary of how the latches are programmed. Note
that the test modes latch is used for factory testing and should
not be programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
Data Latch
C2
C1
0
Control
0
1
R Counter
1
0
N Counter (B)
1
Test Modes
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 18, to allow a wide frequency range
to be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated.
It is important that the correct write sequence be followed at
power-up. The correct write sequence is as follows:
1. R Counter Latch
2. Control Latch
3. N Counter Latch
During band selection, which takes five PFD cycles, the VCO
VTUNE is disconnected from the output of the loop filter and
connected to an internal reference voltage.
0
1.0
0.5
2.5
2.0
1.5
3.5
3.0
80
85
90
100
95
105
115
110
FREQUENCY (MHz)
V
T
UNE
(V)
07139-
019
Figure 18. VTUNE, ADF4360-9, L1 and L2 = 270 nH vs. Frequency
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by the BSC1 bit and the BSC2 bit in the R counter
latch. Where the required PFD frequency exceeds 1 MHz, the
divide ratio should be set to allow enough time for correct band
selection. For many applications, it is usually best to set this to 8.
After band selection, normal PLL action resumes. The value of
KV is determined by the value of the inductors used (see the
Choosing the Correct Inductance Value section). The ADF4360
family contains linearization circuitry to minimize any variation
of the product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
It is strongly recommended that only the 5 mA setting be used.
However, in applications requiring a low VCO frequency, the
high temperature coefficient of some inductors may lead to the
VCO tuning voltage varying as temperature changes. The 7.5 mA
VCO core power setting shows less tuning voltage variation over
temperature in these applications and can be used, provided that
240 resistors are used in parallel with Pin 9 and Pin 10, instead of
the default 470 .
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| ADF4360-9BCPZRL7 | 功能描述:IC SYNTHESIZER W/ADJ VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4360-EVAL | 制造商:Analog Devices 功能描述:INTEGRATED SYNTHESIZER AND VCO - Trays |
| ADF4602 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Chip, Multiband 3G Femtocell Transceiver |
| ADF4602-1XCPZ | 制造商:Analog Devices 功能描述:SINGLE-CHIP, MULTIBAND 3G FEMTOCELL TRANSCEIVER - Rail/Tube |
| ADF4602-1XCPZ-RL | 制造商:Analog Devices 功能描述: |
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