參數(shù)資料
型號(hào)： ADF4360-9BCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/24頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER W/ADJ VCO 24LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類(lèi)型： 扇出配送，整數(shù)-N，合成器（RF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 400MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 帶卷 (TR)
Data Sheet
ADF4360-9
Rev. C | Page 23 of 24
OUTPUT MATCHING
There are a number of ways to match the VCO output of the
ADF4360-9 for optimum operation; the most basic is to use a
51 resistor to VVCO. A dc bypass capacitor of 100 pF is connected
in series, as shown in Figure 33. Because the resistor is not
frequency dependent, this provides a good broadband match.
The output power in the circuit in Figure 33 typically gives
9 dBm output power into a 50 load.
100pF
07139-
030
RFOUT
VVCO
50
51
Figure 33. Simple Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and, therefore, more
output power.
Experiments have shown that the circuit shown in Figure 34
provides an excellent match to 50 over the operating range of
the ADF4360-9. This gives approximately 0 dBm output power
across the specific frequency range of the ADF4360-9 using the
recommended shunt inductor, followed by a 100 pF dc-blocking
capacitor.
L
100pF
07139-
031
RFOUT
VVCO
50
Figure 34. Optimum Output Stage
The recommended value of this inductor changes with the VCO
center frequency. Figure 35 shows a graph of the optimum
inductor value vs. center frequency.
CENTER FREQUENCY (MHz)
INDUC
T
ANCE
(
n
H)
300
250
150
200
100
0
50
0
100
200
300
500
400
07139-
032
Figure 35. Optimum Shunt Inductor vs. Center Frequency
Both complementary architectures can be examined using the
EV-ADF4360-9EB1Z evaluation board. If the user does not
need the differential outputs available on the ADF4360-9, the
user should either terminate the unused output with the same
circuitry as much as possible or combine both outputs using a
balun. Alternatively, instead of the LC balun, both outputs can
be combined using a 180° rat-race coupler.
If the user is only using DIVOUT and does not use the RF
outputs, it is still necessary to terminate both RF output pins
with a shunt inductor/resistor to VVCO and also a dc bypass
capacitor and a 50 load. The circuit in Figure 33 is probably
the simplest and most cost-effective solution. It is important
that the load on each pin be balanced because an unbalanced
load is likely to cause stability problems. Terminations should
be identical as much as possible.
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ADF4360-9BCPZRL7 功能描述:IC SYNTHESIZER W/ADJ VCO 24LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):NJW1504V-TE1-NDNJW1504V-TE1TR
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