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| 型號(hào)： | ADN2807ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類(lèi)型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 帶卷 (TR) |
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ADN2807
Rev. A | Page 4 of 20
Parameter
Conditions
Min
Typ
Max
Unit
PHASE-LOCKED LOOP CHARACTERISTICS
PIN–NIN = 10 mV p-p
Jitter Transfer BW
OC-12
140
200
kHz
OC-3
48
85
kHz
Jitter Peaking
OC-12
0.004
dB
OC-3
0.002
dB
Jitter Generation
OC-12, 12 kHz to 5 MHz
0.003
UI rms
0.02
0.04
UI p-p
OC-3, 12 kHz to 1.3 MHz
0.002
UI rms
0.02
0.04
UI p-p
Jitter Tolerance
OC-12
30 Hz3
100
UI p-p
300 Hz
44
UI p-p
25 kHz
5.8
UI p-p
250 kHz3
1.0
UI p-p
OC-3
30 Hz3
50
UI p-p
300 Hz3
23.5
UI p-p
6500 Hz
6.0
UI p-p
65 kHz3
1.0
UI p-p
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
400
488
540
mV
Differential Output Swing
850
975
1100
mV
Output High Voltage
VOH
VCC
V
Output Low Voltage
VOL, referred to VCC
–0.60
–0.30
V
Rise Time
20% to 80%
150
ps
Fall Time
80% to 20%
150
ps
Setup Time
OC-12
750
ps
OC-3
3145
ps
Hold Time
OC-12
750
ps
OC-3
3150
ps
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
@ REFCLKP or REFCLKN
0
VCC
V
Peak-to-Peak Differential Input
100
mV
Common-Mode Level
DC-coupled, single-ended
VCC/2
V
TEST DATA DC INPUT CHARACTERISTICS4
(TDINP/N)
CML inputs
Peak-to-Peak Differential Input Voltage
0.8
V
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
VIH
2.0
V
Input Low Voltage
VIL
0.8
V
Input Current
VIN = 0.4 V or VIN = 2.4 V
–5
+5
A
Input Current (SEL0 and SEL1 Only)5
VIN = 0.4 V or VIN = 2.4 V
–5
+50
A
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
VOH, IOH = –2.0 mA
2.4
V
Output Low Voltage
VOL, IOL = +2.0 mA
0.4
V
1PIN and NIN should be driven differentially, ac-coupled for optimum sensitivity.
2PWD measurement made on quantizer outputs in BYPASS mode.
3Jitter tolerance measurements are equipment limited.
4TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
5SEL0 and SEL1 have internal pull-down resistors, causing higher IIH.
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