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參數(shù)資料
| 型號(hào)： | ADN2807ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 帶卷 (TR) |
ADN2807
Rev. A | Page 15 of 20
APPLICATION INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane to both analog and
digital grounds is recommended. The VEE pins should be
soldered directly to the ground plane to reduce series
inductance. If the ground plane is an internal plane and
connections to the ground plane are made through vias,
multiple vias may be used in parallel to reduce the series
inductance, especially on Pins 33 and 34, which are the ground
returns for the output buffers.
Use of a 10 F electrolytic capacitor between VCC and GND is
recommended at the location where the 3.3 V supply enters the
PCB. Use of 0.1 F and 1 nF ceramic chip capacitors should be
placed between IC power supply VCC and GND as close as
possible to the ADN2807’s VCC pins. Again, if connections to
the supply and ground are made through vias, the use of
multiple vias in parallel will help to reduce series inductance,
especially on Pins 35 and 36, which supply power to the high
speed CLKOUTP/N and DATAOUTP/N output buffers. Refer
to the schematic in Figure 20 for recommended connections.
Transmission Lines
Use of 50 transmission lines are required for all high
frequency input and output signals to minimize reflections,
including PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and
DATAOUTN (also REFCLKP/N for a 155.52 MHz REFCLK). It
is also recommended that the PIN/NIN input traces are
matched in length and that the CLKOUTP/N and
DATAOUTP/N traces are matched in length. All high speed
CML outputs, CLKOUTP/N and DATAOUTP/N, also require
100 back termination chip resistors connected between the
output pin and VCC. These resistors should be placed as close
as possible to the output pins. These 100 resistors are in
parallel with on-chip 100 termination resistors to create a
50 back termination (Figure 21).
The high speed inputs, PIN and NIN, are internally terminated
with 50 to an internal reference voltage (Figure 22). A 0.1 F
capacitor is recommended between VREF (Pin 4) and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, care should be
taken to keep all high speed digital traces away from sensitive
analog nodes.
Soldering Guidelines for Chip Scale Package
The leads on the 48-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package lead length and 0.05 mm wider than the package lead
width. The land should be centered on the pad. This ensures
that solder joint size is maximized. The bottom of the LFCSP
has a central exposed pad. The pad on the printed circuit board
should be at least as large as this exposed pad. The user must
connect the exposed pad to analog VCC. If vias are used, they
should be incorporated into the pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 oz. copper to plug the via.
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