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參數(shù)資料
| 型號： | ADN2807ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 帶卷 (TR) |
ADN2807
Rev. A | Page 11 of 20
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track the input jitter. In this case,
the VCO control voltage becomes large and saturates, and the
VCO frequency dwells at one or the other extreme of its tuning
range. The size of the VCO tuning range, therefore, has only a
small affect on the jitter accommodation. The delay-locked loop
control voltage is now larger; therefore, the phase shifter takes
on the burden of tracking the input jitter. The phase shifter
range, in UI, can be seen as a broad plateau on the jitter
tolerance curve. The phase shifter has a minimum range of 2 UI
at all data rates.
The gain of the loop integrator is small for high jitter
frequencies, so larger phase differences are needed to make the
loop control voltage big enough to tune the range of the phase
shifter. Large phase errors at high jitter frequencies cannot be
tolerated. In this region, the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small, and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by
the eye opening of the input data, the static phase error, and the
residual loop jitter generation. The jitter accommodation is
roughly 0.5 UI in this region. The corner frequency between the
declining slope and the flat region is the closed loop bandwidth
of the delay-locked loop, which is roughly 5 MHz for OC-12
data rates and 600 kHz for OC-3 data rates.
JITTER PEAKING
IN ORDINARY PLL
ADN2807
Z(s)
X(s)
f (kHz)
JITTER
GAIN
(dB)
o
n psh
d psh
c
03877-0-014
Figure 14. Jitter Response vs. Conventional PLL
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