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參數(shù)資料
| 型號(hào)： | ADN2807ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 帶卷 (TR) |
ADN2807
Rev. A | Page 12 of 20
FUNCTIONAL DESCRIPTION
MULTIRATE CLOCK AND DATA RECOVERY
The ADN2807 recovers clock and data from serial bit streams at
OC-3, OC-12 data rates as well as the 15/14 FEC rates. The
output of the 2.5 GHz VCO is divided down in order to support
the lower data rates. The data rate is selected by the SEL[2..0]
inputs (Table 5).
Table 5. Data Rate Selection
SEL[1..0]
Rate
Frequency (MHz)
00
OC-12
622.08
01
OC-3
155.52
10
OC-12 FEC
666.51
11
OC-3 FEC
166.63
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN) that
are internally terminated with 50 to an on-chip voltage
reference (VREF = 0.6 V typically). These inputs are normally
ac-coupled, although dc-coupling is possible as long as the input
common-mode voltage remains above 0.4 V (Figure 24 to
Figure 26 in the Applications Information section). Input offset
is factory trimmed to achieve better than 4 mV typical
sensitivity with minimal drift. The limiting amplifier can be
driven differentially or single-ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of ASE (amplified spontaneous emission) noise by
applying a differential voltage input of ±0.8 V to SLICEP/N
inputs. If no adjustment of the slice level is needed, SLICEP/N
should be tied to VCC.
LOSS-OF-SIGNAL (LOS) DETECTOR
The receiver front end level signal detect circuit indicates when
the input signal level has fallen below a user adjustable
threshold. The threshold is set with a single external resistor
from THRADJ (Pin 1) to GND. The LOS comparator trip point
versus the resistor value is illustrated in Figure 4 (this is only
valid for SLICEP = SLICEN = VCC). If the input level to the
ADN2807 drops below the programmed LOS threshold,
SDOUT (Pin 45) will indicate the loss-of-signal condition with
a Logic 1. The LOS response time is ~300 ns by design but will
be dominated by the RC time constant in ac-coupled
applications. If the LOS detector is used, the quantizer slice
adjust pins must both be tied to VCC. This is to avoid
interaction with the LOS threshold level.
Note that it is not expected to use both LOS and slice adjust at
the same time. Systems with optical amplifiers need the slice
adjust to evade ASE. However, a loss-of-signal in an optical link
that uses optical amplifiers causes the optical amplifier output
to be full-scale noise. Under this condition, the LOS would not
detect the failure. In this case, the loss-of-lock signal indicates
the failure because the CDR circuitry is unable to lock onto a
signal that is full-scale noise.
REFERENCE CLOCK
There are three options for providing the reference frequency to
the ADN2807: differential clock, single-ended clock, or crystal
oscillator. See Figure 15 to Figure 17 for example configurations.
100k
100k
BUFFER
ADN2807
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
VCC
REFSEL
03877-0-015
Figure 15. Differential REFCLK Configuration
OUT
100k
100k
BUFFER
ADN2807
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
VCC
REFSEL
CLK
OSC
VCC
NC
03877-0-016
Figure 16. Single-Ended REFCLK Configuration
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