參數(shù)資料
型號(hào): ADN2807ACPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 6/20頁
文件大小: 0K
描述: IC CLOCK/DATA RECOVERY 48LFCSP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: SONET/SDH,STM
輸入: CML
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP
包裝: 帶卷 (TR)
ADN2807
Rev. A | Page 14 of 20
50
50
QUANTIZER
+
ADN2807
VREF
NIN
PIN
50
50
VCC
TDINP/N
LOOPEN
BYPASS
CDR
RETIMED
DATA
CLK
0
1
10
DATAOUTP/N
CLKOUTP/N SQUELCH
FROM
QUANTIZER
OUTPUT
03877-0-019
Figure 19. Test Modes
SQUELCH MODE
When the squelch input is driven to a TTL high state, both the
clock and data outputs are set to the zero state to suppress
downstream processing. If desired, this pin can be directly
driven by the LOS (loss-of-signal) detector output (SDOUT). If
the squelch function is not required, the pin should be tied to
VEE.
TEST MODES—BYPASS AND LOOP-BACK
When the bypass input is driven to a TTL high state, the
quantizer output is connected directly to the buffers driving the
data out pins, thus bypassing the clock recovery circuit
(Figure 19). This feature can help the system to deal with
nonstandard bit rates.
The loopback mode can be invoked by driving the LOOPEN
pin to a TTL high state, which facilitates system diagnostic
testing. This will connect the test inputs (TDINP/N) to the
clock and data recovery circuit (per Figure 19). The test inputs
have internal 50 terminations and can be left floating when
not in use. TDINP/N are CML inputs and can be dc-coupled
only when being driven by CML outputs. The TDINP/N inputs
must be ac-coupled if driven by anything other than CML
outputs. Bypass and loop-back modes are mutually exclusive;
only one of these modes can be used at any given time. The
ADN2807 is put into an indeterminate state if both BYPASS
and LOOPEN pins are set to Logic 1 at the same time.
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