Do Until Loop [IF cond] JUMP (Ix) ; Jump [IF cond] JUMP &" />
參數(shù)資料
型號(hào)： ADSP-2101BG-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/64頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 68PGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類(lèi)型： 定點(diǎn)
接口： 同步串行端口（SSP）
時(shí)鐘速率： 25MHz
非易失內(nèi)存： 外部
芯片上RAM： 6kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 通孔
封裝/外殼： 68-BEPGA
供應(yīng)商設(shè)備封裝： 68-PGA（27.89x27.89）
包裝： 托盤(pán)
ADSP-21xx
–16–
REV. B
Program Flow Instructions
DO <addr> [UNTIL term] ;
Do Until Loop
[IF cond] JUMP (Ix) ;
Jump
[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;
Call Subroutine
[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN
JUMP <addr>;
Jump/Call on Flag In Pin
IF [NOT ] FLAG_IN
CALL <addr>;
[IF cond] SET|RESET|TOGGLE
FLAG_OUT [, ...] ;
Modify Flag Out Pin
[IF cond] RTS ;
Return from Subroutine
[IF cond] RTI ;
Return from Interrupt Service Routine
IDLE [(n)] ;
Idle
Miscellaneous Instructions
NOP ;
No Operation
MODIFY (Ix , My);
Modify Address Register
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;
Stack Control
ENA|DIS
SEC_REG [, ...] ;
Mode Control
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0* MY1 ( RND), MX0=DM(I2,M1);
{ MF=error * beta}
MR=MX0* MF ( RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:
PM(I6,M6)= A R, MR=MX0 * MF ( RND);
MODIFY(I2,M3);
{Point to oldest data}
MODIFY(I6,M7);
{Point to start of data}
Notation Conventions
Ix
Index registers for indirect addressing
My
Modify registers for indirect addressing
<data>
Immediate data value
<addr>
Immediate address value
<exp>
Exponent (shift value) in shift immediate instructions (8-bit signed number)
<ALU>
Any ALU instruction (except divide)
<MAC>
Any multiply-accumulate instruction
<SHIFT>
Any shift instruction (except shift immediate)
cond
Condition code for conditional instruction
term
Termination code for DO UNTIL loop
dreg
Data register (of ALU, MAC, or Shifter)
reg
Any register (including dregs)
;
A semicolon terminates the instruction
,
Commas separate multiple operations of a single instruction
[
]
Optional part of instruction
[, ...]
Optional, multiple operations of an instruction
option1 | option2
List of options; choose one.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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