Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry" />
參數(shù)資料
型號： ADSP-21065LKSZ-240
廠商： Analog Devices Inc
文件頁數(shù)： 6/44頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLR 544KBIT 208MQFP
產(chǎn)品培訓模塊： SHARC Processor Overview
標準包裝： 1
系列： SHARC®
類型： 浮點
接口： 主機接口，串行端口
時鐘速率： 60MHz
非易失內存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-MQFP（28x28）
包裝： 托盤
其它名稱： ADSP-21065LKSZ240
ADSP-21065LKSZ240-ND
REV. C
ADSP-21065L
–14–
Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor
will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device con-
nected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read opera-
tion. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
66 MHz
60 MHz
Parameter
Min
Max
Min
Max
Unit
Clock Input
Timing Requirements:
tCK
CLKIN Period
30.00
100
33.33
100
ns
tCKL
CLKIN Width Low
7.0
ns
tCKH
CLKIN Width High
5.0
ns
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
3.0
ns
CLKIN
tCKH
tCK
tCKL
Figure 7. Clock Input
Parameter
Min
Max
Unit
Reset
Timing Requirements:
tWRST
RESET Pulsewidth Low1
2 tCK
ns
tSRST
RESET Setup Before CLKIN High2
23.5 + 24 DT tCK
ns
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 3000 CLKIN cycles while
RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after
reset.
CLKIN
RESET
tWRST
tSRST
Figure 8. Reset
Parameter
Min
Max
Unit
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup Before CLKIN High or Low1
11.0 + 12 DT
ns
tHIR
IRQ2-0 Hold Before CLKIN High or Low1
0.0 + 12 DT
ns
tIPW
IRQ2-0 Pulsewidth2
2.0 + tCK/2
ns
NOTES
1Only required for
IRQx recognition in the following cycle.
2Applies only if t
SIR and tHIR requirements are not met.
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