- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19401 > ADSP-21478KCPZ-1A (Analog Devices Inc)IC DSP SHARK 200MHZ 88LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADSP-21478KCPZ-1A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SHARK 200MHZ 88LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | ROM（4Mb） |
| 芯片上RAM： | 3Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
Rev. C
|
Page 16 of 76
|
July 2013
PIN FUNCTION DESCRIPTIONS
Table 11. Pin Descriptions
Name
Type
State During/
After Reset
Description
ADDR23–0
I/O/T (ipu)
High-Z/driven
low (boot)
External Address. The processor outputs addresses for external memory and
peripherals on these pins. The ADDR pins can be multiplexed to support the
external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all
ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR23–4
pins for parallel input data.
DATA15–0
I/O/T (ipu)
High-Z
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O) and FLAGS7–0 (I/O).
AMI_ACK
I (ipu)
Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait
states to an external memory access. AMI_ACK is used by I/O devices, memory
controllers, or other peripherals to hold off completion of an external memory
access.
MS0–1
O/T (ipu)
High-Z
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the
corresponding banks of external memory. The MS1-0 lines are decoded memory
address lines that change at the same time as the other address lines. When no
external memory access is occurring the MS1-0 lines are inactive; they are active
however when a conditional memory access instruction is executed, when the
condition evaluates as true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information on
processor booting, see the ADSP-214xx SHARC Processor Hardware Reference.
AMI_RD
O/T (ipu)
High-Z
AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word
from external memory.
AMI_WR
O/T (ipu)
High-Z
AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to
external memory.
FLAG0/IRQ0
I/O (ipu)
FLAG[0] INPUT
FLAG0/Interrupt Request0.
FLAG1/IRQ1
I/O (ipu)
FLAG[1] INPUT
FLAG1/Interrupt Request1.
FLAG2/IRQ2/MS2
I/O (ipu)
FLAG[2] INPUT
FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2
in the 196-ball BGA package only.
FLAG3/TMREXP/MS3
I/O (ipu)
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the
196-ball BGA package only.
The following symbols appear in the Type column of Table 11: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The
range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions
the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on
Page 70.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-22M-CY-F3 | CONVERTER MOD DC/DC 10V 50W |
| 5703-RC | CHOKE RF HI CURR 125UH 15% RAD |
| VI-22L-CY-F4 | CONVERTER MOD DC/DC 28V 50W |
| EBM08DRXH | CONN EDGECARD 16POS DIP .156 SLD |
| RS-4815D | CONV DC/DC 2W 36-72VIN +/-15VOUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21478KSWZ-1A | 功能描述:IC DSP SHARC 200MHZ LP 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21478KSWZ-2A | 功能描述:IC DSP SHARC 266MHZ LP 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21478KSWZ-ENG | 制造商:Analog Devices 功能描述:SHARC PROCESSOR - Trays |
| ADSP-21479 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21479BBCZ-2A | 功能描述:IC DSP SHARC 266MHZ LP 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。