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參數(shù)資料
| 型號： | ADSP-21478KSWZ-2A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SHARC 266MHZ LP 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 266MHz |
| 非易失內(nèi)存： | ROM（4Mb） |
| 芯片上RAM： | 3Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP-EP（14x14） |
| 包裝： | 托盤 |
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Rev. A
|
Page 24 of 72
|
September 2011
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 18. While no specific power-up sequencing is required
between VDD_EXT and VDD_INT, there are some considerations
that the system designs should take into account.
No power supply should be powered up for an extended
period of time (>200 ms) before another supply starts to
ramp up.
If the VDD_INT power supply comes up after VDD_EXT, any
pin, such as RESETOUT and RESET, may actually drive
momentarily until the VDD_INT rail has powered up. Systems
sharing these signals on the board must determine if there
are any issues that need to be addressed based on this
behavior.
Note that during power-up, when the VDD_INT power supply
comes up after VDD_EXT, a leakage current of the order of three-
state leakage current pull-up, pull-down, may be observed on
any pin, even if that is an input only (for example, the RESET
pin), until the VDD_INT rail has powered up.
Figure 5. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
PCLK
SDRAM
DIVIDER
BYPASS
MUX
PMCTL
(SDCKR)
CCLK
PLL
XTAL
CLKIN
DIVIDER
RESET
f
VCO ÷ (2 × PLLM)
BUF
VCO
BUF
PMCTL
(INDIV)
PLL
DIVIDER
RESETOUT
CLKOUT (TEST ONLY)*
DELAY OF
4096 CLKIN
CYCLES
PCLK
PMCTL
(PLLBP)
PMCTL
(PLLD)
f
VCO
f
CCLK
fINPUT
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f
INPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
CLK_CFGx/
PMCTL (2 × PLLM)
DIVIDE
BY 2
PIN
MUX
PMCTL
(PLLBP)
CCLK
RESETOUT
CORESRST
SDCLK
BYPASS
MUX
Table 18. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before VDD_EXT or VDD_INT On
0
ms
tIVDDEVDD
VDD_INT On Before VDD_EXT
–200
+200
ms
tCLKVDD
1
CLKIN Valid After VDD_INT and VDD_EXT Valid
0
200
ms
tCLKRST
CLKIN Valid Before RESET Deasserted
10
2
ms
tPLLRST
PLL Control Setup Before RESET Deasserted
20
3
ms
Switching Characteristic
tCORERST
Core Reset Deasserted After RESET Deasserted
4096 × tCK + 2 × tCCLK
4, 5
ms
1 Valid VDD_INT and VDD_EXT assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary
from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Based on CLKIN cycles.
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5 The 4096 cycle count depends on tSRST specification in Table 20. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
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| ADSP-21479 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21479BBCZ-2A | 功能描述:IC DSP SHARC 266MHZ LP 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21479BBCZ-2AX | 制造商:Analog Devices 功能描述:- Trays |
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