參數(shù)資料
型號: ADSP-21478KSWZ-2A
廠商: Analog Devices Inc
文件頁數(shù): 19/72頁
文件大?。?/td> 0K
描述: IC DSP SHARC 266MHZ LP 100LQFP
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI,EBI/EMI,I²C,SPI,SPORT,UART/USART
時(shí)鐘速率: 266MHz
非易失內(nèi)存: ROM(4Mb)
芯片上RAM: 3Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-LQFP-EP(14x14)
包裝: 托盤
Rev. A
|
Page 26 of 72
|
September 2011
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in Table 10. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 8 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Reset
Figure 8. 266 MHz Operation (Fundamental Mode Crystal)
C1
22pF
Y1
R1
1MΩ *
XTAL
CLKIN
C2
22pF
16.67
R2
47Ω *
ADSP-2147x
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Table 20. Reset
Parameter
Min
Max
Unit
Timing Requirements
tWRST
1
RESET Pulse Width Low
4 × tck
ns
tSRST
RESET Setup Before CLKIN Low
8
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100
μs while RESET is low, assuming stable
Vdd and CLKIN (not including start-up time of external clock oscillator).
Figure 9. Reset
CLKIN
RESET
tSRST
tWRST
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