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參數(shù)資料
| 型號： | ADSP-21478KSWZ-2A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SHARC 266MHZ LP 100LQFP |
| 標準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 時鐘速率： | 266MHz |
| 非易失內(nèi)存： | ROM（4Mb） |
| 芯片上RAM： | 3Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP-EP（14x14） |
| 包裝： | 托盤 |
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Rev. A
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Page 10 of 72
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September 2011
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface ports (SPI), one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), three PWM modules (PWM3–1), and two general-
purpose timers.
Serial Peripheral (Compatible) Interface (SPI)
The SPI is an industry-standard synchronous serial link,
enabling the SPI-compatible port to communicate with other
SPI compatible devices. The SPI consists of two data pins, one
device select pin, and one clock pin. It is a full-duplex synchro-
nous serial interface, supporting both master and slave modes.
The SPI port can operate in a multimaster environment by
interfacing with up to four other SPI-compatible devices, either
acting as a master or slave device. The SPI-compatible periph-
eral implementation also features programmable baud rate and
clock phase and polarities. The SPI-compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for 5 to 8 data
bits, 1 or 2 stop bits, and none, even, or odd parity. The UART
port supports two modes of operation:
PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
Support for bit rates ranging from (fPCLK/1,048,576) to
(fPCLK/16) bits per second.
Support for data formats from 7 to 12 bits per frame.
Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
generating 16 PWM outputs in total. Each PWM group pro-
duces two pairs of PWM signals on the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
midpoint of the PWM period. In double update mode, a second
updating of the PWM registers is implemented at the midpoint
of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis-
tortion in three-phase PWM inverters.
PWM signals can be mapped to the external port address lines
or to the DPI pins.
Timers
The processors have a total of three timers: a core timer that can
generate periodic software interrupts and two general-purpose
timers that can generate periodic interrupts and be indepen-
dently set to operate in one of three modes:
Pulse waveform generation mode
Pulse width count/capture mode
External event watch dog mode
The core timer can be configured to use FLAG3 as a timer
expired signal, and the general-purpose timers have one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables the general-
purpose timer.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
7-bit addressing
Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
Digital filtering and timed event processing
100 kbps and 400 kbps data rates
Low interrupt rate
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