參數(shù)資料
型號(hào): ADSP-2185LBSTZ-210
廠商: Analog Devices Inc
文件頁(yè)數(shù): 29/48頁(yè)
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類(lèi)型: 定點(diǎn)
接口: 主機(jī)接口,串行端口
時(shí)鐘速率: 52MHz
非易失內(nèi)存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤(pán)
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C
|
Page 35 of 48
|
January 2008
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 25. IDMA Read, Short Read Cycle in Short Read Only Mode1
Parameter
2
Min
Max
Unit
Timing Requirements:
tIKR
IACK Low Before Start of Read3
0ns
tIRP
Duration of Read4
10
ns
Switching Characteristics:
tIKHR
IACK High After Start of Read
10
ns
tIKDH
IAD15 – 0 Previous Data Hold After End of Read
0ns
tIKDD
IAD15 – 0 Previous Data Disabled After End of Read
10
ns
tIRDE
IAD15 – 0 Previous Data Enabled After Start of Read
0
ns
tIRDV
IAD15 – 0 Previous Data Valid After Start of Read
10
ns
1 Applies to the ADSP-2187L only.
2 Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by
an external host writing to the register. Disabled by default.
3 Start of Read = IS Low and IRD Low. Previous data remains until end of read.
4 End of Read = IS High or IRD High.
Figure 27. IDMA Read, Short Read Cycle in Short Read Only Mode
tIRP
tIKR
PR EVIO U S
DATA
tIKHR
tIR DV
tIKDD
tIRDE
tIKDH
IA D 15–0
IA CK
IS
IRD
LEG EN D :
IM PL IES TH A T
IS AND IR D CAN BE
H E LD INDE FINITE LY BY HO S T
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