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參數(shù)資料
| 型號： | ADSP-2185LBSTZ-210 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 45/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 52MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 80kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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Rev. C
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Page 6 of 48
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January 2008
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Individual interrupt requests are logically AND’ed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
ADSP-218xL series members mask all interrupts for one
instruction cycle following the execution of an instruction that
modifies the IMASK register. This does not affect serial port
autobuffering or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are 12 levels deep to allow interrupt, loop, and subroutine nest-
ing. The following instructions allow global enable or disable
servicing of the interrupts (including power-down), regardless
of the state of IMASK:
ENA INTS;
DIS INTS;
Disabling the interrupts does not affect serial port autobuffering
or DMA. When the processor is reset, interrupt servicing
is enabled.
LOW POWER OPERATION
ADSP-218xL series members have three low-power modes that
significantly reduce the power dissipation when the device oper-
ates under standby conditions. These modes are:
Power-Down
Idle
Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
ADSP-218xL series members have a low-power feature that lets
the processor enter a very low-power dormant state through
hardware or software control. Following is a brief list of power-
down features. Refer to the ADSP-218x DSP Hardware Refer-
ence, “System Interface” chapter, for detailed information about
the power-down feature.
Quick recovery from power-down. The processor begins
executing instructions in as few as 400 CLKIN cycles.
Support for an externally generated TTL or CMOS proces-
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
400 CLKIN cycle recovery.
Support for crystal operation includes disabling the oscilla-
tor to save power (the processor automatically waits
approximately 4096 CLKIN cycles for the crystal oscillator
to start or stabilize), and letting the oscillator run to allow
400 CLKIN cycle start-up.
Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The power-
down interrupt also can be used as a nonmaskable, edge-
sensitive interrupt.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving
the power-down state.
The RESET pin also can be used to terminate power-down.
Power-down acknowledge pin (PWDACK) indicates when
the processor has entered power-down.
Idle
When the ADSP-218xL is in the Idle Mode, the processor waits
indefinitely in a low-power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle Mode IDMA, BDMA, and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on ADSP-218xL series mem-
bers to let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, ADSP-218xL series members
remain in the idle state for up to a maximum of n processor
cycles (n = 16, 32, 64, or 128) before resuming
normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
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