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| 型號(hào)： | ADSP-2185LBSTZ-210 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，串行端口 |
| 時(shí)鐘速率： | 52MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 80kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C
|
Page 7 of 48
|
January 2008
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xL series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xL series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
Clock Signals
ADSP-218xL series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal oper-
ation. The only exception is while the processor is in the
power-down state. For additional information, refer to the
ADSP-218x DSP Hardware Reference, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
ADSP-218xL series members use an input clock with a fre-
quency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single pro-
cessor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xL series members include an on-chip oscil-
lator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 3. Capacitor values are
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in Figure 3.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
Figure 2. Basic System Interface
In
ser
t s
yst
em
in
ter
fac
e d
iag
ram
he
re
1/2
CLOCK
OR
CRYSTA L
FL0–2
CLKIN
XTAL
SERIAL
DEVICE
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
SERIAL
DEVICE
A0–A21
DATA
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
DATA
ADDR
DATA
ADDR
2048 LOCATIONS
OVERLAY
MEMORY
TWO 8K
PM SEGMEN TS
D23–0
A13–0
D23–8
A10–0
D15–8
D23–16
A13–0
14
24
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
DATA23–0
ADSP-218xL
CS
1/2
CLOCK
OR
CRYSTAL
CLK IN
XTAL
FL0–2
SERIAL
DEVIC E
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
16
IDMA PORT
IRD/D6
IS/D4
IAL/D5
IACK/D3
IAD15-0
SERIAL
DEVICE
SC LK0
RFS0
TFS0
DT0
DR0
SPORT0
1
16
A0
DATA23–8
IOMS
BMS
DMS
CMS
BR
BG
BGH
PWD
PW DACK
HOST MEMOR Y MODE
FULL MEMORY MODE
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
WR
RD
SYSTEM
INTERFAC E
OR
C ONTRO LLER
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
IOMS
BMS
PMS
CMS
BR
BG
BGH
PWD
PW DACK
WR
RD
AD SP-218xL
DMS
TW O 8K
DM SEGMEN TS
PMS
ADDR13–0
IRQL1/PF6
IWR/D7
NOTE: MO D E D APPLIES TO THE AD SP-2187L P RO CES SOR ON LY
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