REV. 0
ADSP-2188M
–35–
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle in Short Read Only Mode
1
Timing Requirements:
tIKR
IACK Low before Start of Read2
0ns
tIRP
Duration of Read
3
10
ns
Switching Characteristics:
tIKHR
IACK High after Start of Read2
10
ns
tIKDH
IAD15–0 Previous Data Hold after End of Read
3
0ns
tIKDD
IAD15–0 Previous Data Disabled after End of Read
3
10
ns
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
0
ns
tIRDV
IAD15–0 Previous Data Valid after Start of Read
10
ns
NOTES
1Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the
register or by an external host writing to the register. Disabled by default.
2Start of Read =
IS Low and IRD Low. Previous data remains until end of read.
3End of Read =
IS High or IRD High.
tIRP
tIKR
PREVIOUS
DATA
tIKHR
tIRDV
tIKDD
tIRDE
tIKDH
IAD15–0
IACK
IS
IRD
Figure 32. IDMA Read, Short Read Only Cycle