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| 型號： | ADSP-2188MBSTZ-266 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 66MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 256kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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REV. 0
ADSP-2188M
–15–
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with wait
states set by BMWAIT. These accesses continue until the count
reaches zero. When enough accesses have occurred to create a
destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
The BMWAIT field, which has 4 bits on ADSP-2188M, allows
selection up to 15 wait states for BDMA transfers.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2188M. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer
2. Host checks
IACK control line to see if the DSP is busy
3. Host uses
IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers. If Bit 15 = 1, the
value of bits 7:0 represent the IDMA overlay: bits 14:8 must
be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent the
starting address of internal memory to be accessed and
Bit 14 reflects PM or DM for access.
4. Host uses
IS and IRD (or IWR) to read (or write) DSP inter-
nal memory (PM or DM).
5. Host checks
IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written while the ADSP-2188M
is operating at full speed.
The DSP memory address is latched and then automatically incre-
mented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (
IS) latches
this value into the IDMAA register.
Once the address is stored, data can be read from, or written to,
the ADSP-2188M’s on-chip memory. Asserting the select line
(
IS) and the appropriate read or write line (IRD and IWR
respectively) signals the ADSP-2188M that a particular transac-
tion is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (
IS) and address latch enable (IAL) directs
the ADSP-2188M to write the address onto the IAD0–14 bus
into the IDMA Control Register. If Bit 15 is set to 0, IDMA
latches the address. If Bit 15 is set to 1, IDMA latches into the
OVLAY register. This register, shown below, is memory mapped
at address DM (0x3FE0). Note that the latched address (IDMAA)
cannot be read back by the host. When Bit 14 in 0x3FE7 is set
to 1, timing in Figure 31 applies for short reads. When Bit 14
in 0x3FE7 is set to zero, short reads use the timing shown in Fig-
ure 32.
Refer to the following figures for more information on IDMA
and DMA memory maps.
IDMA OVERLAY
DM (0x3FE7)
RESERVED SET TO 0
IDDMOVLAY
IDPMOVLAY
0
0000
0
15 14 13 12 11 10
9
8
7
6
5
43210
SHORT READ ONLY
0 = ENABLE
1 = DISABLE
IDMA CONTROL (U = UNDEFINED AT RESET)
DM (0x3FE0)
IDMAA ADDRESS
U
UUUU
UUUUU
U
15 14 13 12 11 10
9
8
7
6
5
43210
IDMAD DESTINATION MEMORY TYPE
0 = PM
1 = DM
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
0
RESERVED SET TO 0
0
RESERVED SET TO 0
Figure 10. IDMA Control/OVLAY Registers
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