參數(shù)資料
型號： ADSP-2189MKSTZ-300
廠商： Analog Devices Inc
文件頁數(shù)： 27/32頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 100-LQFP
標準包裝： 1
系列： ADSP-21xx
類型： 定點
接口： 主機接口，串行端口
時鐘速率： 75MHz
非易失內(nèi)存： 外部
芯片上RAM： 192kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
其它名稱： ADSP-2189MKSTZ300
ADSP-2189MKSTZ300-ND
REV. A
ADSP-2189M
–4–
functionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics.
Common-Mode Pins
Pin
# of
Name(s)
Pins I/O Function
RESET
1
I
Processor Reset Input
BR
1
I
Bus Request Input
BG
1
O
Bus Grant Output
BGH
1
O
Bus Grant Hung Output
DMS
1
O
Data Memory Select Output
PMS
1
O
Program Memory Select Output
IOMS
1
O
Memory Select Output
BMS
1
O
Byte Memory Select Output
CMS
1
O
Combined Memory Select Output
RD
1
O
Memory Read Enable Output
WR
1
O
Memory Write Enable Output
IRQ2
1
I
Edge- or Level-Sensitive Interrupt
Requests
1
PF7
I/O Programmable I/O Pin.
IRQL1
1
I
Level-Sensitive Interrupt Requests
1
PF6
I/O Programmable I/O Pin
IRQL0
1
I
Level-Sensitive Interrupt Requests
1
PF5
I/O Programmable I/O Pin
IRQE
1
I
Edge-Sensitive Interrupt Requests
1
PF4
I/O Programmable I/O Pin
Mode D
1
I
Mode Select Input—Checked Only
During
RESET
PF3
I/O Programmable I/O Pin During
Normal Operation
Mode C
1
I
Mode Select Input—Checked Only
During
RESET
PF2
I/O Programmable I/O Pin During
Normal Operation
Mode B
1
I
Mode Select Input—Checked
Only During
RESET
PF1
I/O Programmable I/O Pin During
Normal Operation
Mode A
1
I
Mode Select Input—Checked Only
During
RESET
PF0
I/O Programmable I/O Pin During
Normal Operation
CLKIN, XTAL 2
I
Clock or Quartz Crystal Input
CLKOUT
1
O
Processor Clock Output
SPORT0
5
I/O Serial Port I/O Pins
SPORT1
5
I/O Serial Port I/O Pins
IRQ1:0, FI, FO
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out
2
PWD
1
I
Power-Down Control Input
PWDACK
1
O
Power-Down Control Output
FL0, FL1, FL2 3
O
Output Flags
VDDINT
2
I
Internal VDD (2.5 V) Power
VDDEXT
4
I
External VDD (2.5 V or 3.3 V)
Power
GND
10
I
Ground
EZ-Port
9
I/O For Emulation Use
NOTES
1Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, then the DSP will vector to the appropri-
ate interrupt vector address when the pin is asserted, either by external devices,
or set as a programmable flag.
2SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
Memory Interface Pins
The ADSP-2189M processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during
RESET and cannot be changed while
the processor is running.
Full Memory Mode Pins (Mode C = 0)
Pin
# of
Name
Pins
I/O
Function
A13:0
14
O
Address Output Pins for Program,
Data, Byte and I/O Spaces
D23:0
24
I/O
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses.)
Host Mode Pins (Mode C = 1)
Pin
# of
Name
Pins
I/O
Function
IAD15:0
16
I/O
IDMA Port Address/Data Bus
A0
1
O
Address Pin for External I/O,
Program, Data, or Byte Access
1
D23:8
16
I/O
Data I/O Pins for Program, Data
Byte and I/O Spaces
IWR
1
I
IDMA Write Enable
IRD
1
I
IDMA Read Enable
IAL
1
I
IDMA Address Latch Pin
IS
1
I
IDMA Select
IACK
1
O
IDMA Port Acknowledge Config-
urable in Mode D; Open Drain
NOTE
1In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2189M provides four dedicated external interrupt
input pins,
IRQ2, IRQL0, IRQL1 and IRQE (shared with the
PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-2189M also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter-
rupt levels are internally prioritized and individually maskable
(except power-down and reset). The
IRQ2, IRQ0 and IRQ1
input pins can be programmed to be either level- or edge-sensi-
tive.
IRQL0 and IRQL1 are level-sensitive and IRQE is edge-
sensitive. The priorities and vector addresses of all interrupts are
shown in Table I.
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