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參數(shù)資料
| 型號： | ADSP-2189MKSTZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/32頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100-LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 75MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 192kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ADSP-2189MKSTZ300 ADSP-2189MKSTZ300-ND |
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REV. A
ADSP-2189M
–8–
Mode D = 1 and in host mode:
IACK is an open source and
requires an external pull-down, but multiple
IACK pins can be
wire OR-ed together.
MEMORY ARCHITECTURE
The ADSP-2189M provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
ADSP-2189M.
Program Memory
Program Memory, Full Memory Mode is a 24-bit-wide space
for storing both instruction op codes and data. The ADSP-2189M
has 32K words of Program Memory RAM on chip and the
capability of accessing up to two 8K external memory overlay
spaces using the external data bus.
Program Memory, Host Mode allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.
Table III. PMOVLAY Bits
PMOVLAY
Memory
A13
A12:0
0, 4, 5
Internal
Not Applicable Not Applicable
1
External
0
13 LSBs of Address
Overlay 1
Between 0x2000
and 0x3FFF
2
External
1
13 LSBs of Address
Overlay 2
Between 0x2000
and 0x3FFF
Data Memory
Data Memory, Full Memory Mode is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2189M has 48K words on Data
Memory RAM on-chip. Part of this space is used by 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All inter-
nal accesses complete in one cycle. Accesses to external memory
are timed using the wait-states specified by the DWAIT register
and the wait-state mode bit.
ACCESSIBLE WHEN
DMOVLAY = 2
ACCESSIBLE WHEN
DMOVLAY = 1
0 0000–
0 1FFF
0 0000–
0 1FFF
EXTERNAL
MEMORY
32 MEMORY–
MAPPED
REGISTERS
0 3FFF
0 2000
0 1FFF
INTERNAL
8160
WORDS
0 0000
DATA MEMORY
ADDRESS
INTERNAL
MEMORY
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7
OR
EXTERNAL 8K
DMOVLAY = 1, 2
0 3FE0
0 3FDF
DATA MEMORY
ACCESSIBLE WHEN
DMOVLAY = 7
ACCESSIBLE WHEN
DMOVLAY = 6
0 0000–
0 1FFF
0 0000–
0 1FFF
ACCESSIBLE WHEN
DMOVLAY = 5
ALWAYS
ACCESSIBLE
AT ADDRESS
0 2000 – 0 3FFF
ACCESSIBLE WHEN
DMOVLAY = 0
ACCESSIBLE WHEN
DMOVLAY = 4
0 0000–
0 1FFF
0 0000–
0 1FFF
0 0000–
0 1FFF
Figure 5. Data Memory Map
ACCESSIBLE WHEN
PMOVLAY = 2
ACCESSIBLE WHEN
PMOVLAY = 1
ACCESSIBLE WHEN
PMOVLAY = 5
ALWAYS
ACCESSIBLE
AT ADDRESS
0 0000 – 0 1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
ACCESSIBLE WHEN
PMOVLAY = 4
INTERNAL
MEMORY
EXTERNAL
MEMORY
0 2000–
0 3FFF
0 2000–
0 3FFF
0 2000–
0 3FFF
0 2000–
0 3FFF2
0 2000–
0 3FFF2
PM (MODE B = 0)
8K INTERNAL
PMOVLAY = 0
8K EXTERNAL
PROGRAM MEMORY
MODE B = 1
ADDRESS
0 3FFF
0 2000
0 1FFF
0 0000
8K INTERNAL
PMOVLAY = 0, 4, 5
OR
8K EXTERNAL
PMOVLAY = 1, 2
0 3FFF
0 2000
0 1FFF
8K INTERNAL
0 0000
PROGRAM MEMORY
MODE B = 0
ADDRESS
ACCESSIBLE WHEN
PMOVLAY = 1
RESERVED
INTERNAL
MEMORY
EXTERNAL
MEMORY
0 2000–
0 3FFF
0 0000–
0 1FFF2
PM (MODE B = 1)1
RESERVED
1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2SEE TABLE III FOR PMOVLAY BITS
ACCESSIBLE WHEN
PMOVLAY = 0
RESERVED
0 0000–
0 1FFF2
Figure 4. Program Memory
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