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參數資料
| 型號： | ADSP-2189MKSTZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 5/32頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100-LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 75MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 192kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ADSP-2189MKSTZ300 ADSP-2189MKSTZ300-ND |
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REV. A
ADSP-2189M
–13–
The ICE-Port interface consists of the following ADSP-2189M
pins:
EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,
and ELOUT.
These ADSP-2189M pins must be connected only to the EZ-
ICE connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2189M and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE:
BR, BG,
RESET, and GND.
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2189M in the target system. This causes the
processor to use its
ERESET, EBR, and EBG pins instead of
the
RESET, BR, and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 13. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
12
34
56
78
9
10
11
12
13
14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
Figure 13. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1
× 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM, and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in this data sheet. The performance of the EZ-ICE
may approach published worst case specification for some memory
access timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction: All memory strobe signals on the ADSP-2189M
(
RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your
target system must have 10 k
pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
RESET
signal.
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
BR signal.
EZ-ICE emulation ignores
RESET and BR when single-
stepping.
EZ-ICE emulation ignores
RESET and BR when in Emula-
tor Space (DSP halted).
EZ-ICE emulation ignores the state of target
BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (
BG) is as-
serted by the EZ-ICE board’s DSP.
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