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| 型號： | ADSP-21992BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 176LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | SPI，SSP |
| 時鐘速率： | 160MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP |
| 供應(yīng)商設(shè)備封裝： | 176-LQFP（24x24） |
| 包裝： | 托盤 |
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Rev. A
|
Page 4 of 60
|
August 2007
ADSP-21992
an algebraic syntax for ease of coding and readability. A com-
prehensive set of development tools supports program
development.
The block diagram (Figure 2) shows the architecture of the
embedded SHARC core. It contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from
the register file and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.
Register usage rules influence placement of input and results
within the computational units. For most operations, the data
registers of the computational units act as a data register file,
permitting any input or result register to provide input to any
unit for a computation. For feedback operations, the computa-
tional units let the output (result) of any unit be input to any
unit on the next cycle. For conditional or multifunction instruc-
tions, there are restrictions on which data registers may provide
inputs or receive results from each computational unit. For
more information, see the ADSP-2199x DSP Instruction Set
Reference.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-21992 executes looped code
with zero overhead; no explicit jump instructions are required
to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four 16-bit
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is pre- or post-modified by the value of
one of four possible modify registers. A length value and base
address may be associated with each pointer to implement auto-
matic modulo addressing for circular buffers. Page registers in
the DAGs allow circular addressing within 64K word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the pri-
mary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
Program memory address (PMA) bus
Program memory data (PMD) bus
Data memory address (DMA) bus
Data memory data (DMD) bus
Direct memory access address bus
Direct memory access data bus
Figure 2. Block Diagram
DATA
ADDRESS
B
L
O
C
K
3
DATA
ADDRESS
B
L
O
C
K
2
SYSTEM INTERRUPT
CONTROLLER
I/O DATA
I/O REGISTERS
(MEMORY-MAPPED)
CONTROL
STATUS
BUFFERS
I/O PROCESSOR
CACHE
64
24-BIT
JTAG
TEST AND
EMULATION
6
ADDR BUS
MUX
DATA BUS
MUX
16
20
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
PX
24
16
ADSP-219x DSP CORE
PROGRAM
SEQUENCER
DATA
REGISTER
FILE
MULT
BARREL
SHIFTER
ALU
DMA CONTROLLER
INPUT
REGISTERS
RESULT
REGISTERS
16
16-BIT
INTERNAL MEMORY
24
ADDRESS
B
L
O
C
K
1
DATA
ADDRESS
B
L
O
C
K
0
24 BIT
16 BIT
FOUR INDEPENDENT BLOCKS
PROGRAMMABLE
FLAGS (16)
TIMERS
(3)
3
DMA CONNECT
DMA ADDRESS
EXTERNAL PORT
24 BIT
18
I/O ADDRESS
24
16
24
DMA DATA
EMBEDDED
CONTROL
PERIPHERALS
AND
COMMUNICATIONS
PORTS
DAG1
4
16
DAG2
4
16
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| ADSP-21992YBC | 功能描述:IC DSP CTLR 16BIT 196CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21992YST | 制造商:Analog Devices 功能描述: |
| ADSP-21BT101JST | 制造商:Analog Devices 功能描述: |
| ADSP21CSP01BS200 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP21CSP01KS200 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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