參數(shù)資料
型號(hào)： ADSP-BF548MBBCZ-5M
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/100頁(yè)
文件大?。?/td> 0K
描述： IC DSP 533MHZ W/DDR 400CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： CAN，SPI，SSP，TWI，UART，USB
時(shí)鐘速率： 533MHz
非易失內(nèi)存： 外部
芯片上RAM： 260kB
電壓 - 輸入/輸出： 2.50V，3.30V
電壓 - 核心： 1.25V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 400-CSPBGA（17x17）
包裝： 托盤(pán)
配用： ADSP-3PARCBF548M01-ND - MODULE BOARD BF548
ADSP-3PARCBF548E02-ND - KIT DEV STARTER BF548
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 35 of 100
|
February 2010
Table 13 and Table 16 describe the voltage/frequency require-
ments for the ADSP-BF54x Blackfin processors’ clocks. Take
care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock. Table 15
describes the phase-locked loop operating conditions.
7 Parameter value applies to pins DQ0–15 and DQS0–1.
8 PB1-0, PE15-14, PG15-11, and PH7-6 are 5.0 V-tolerant (always accept up to 5.5 V maximum V
IH when power is applied to VDDEXT pins). Voltage compliance (on output
VOH) is limited by VDDEXT supply voltage.
9 SDA and SCL are 5.0V tolerant (always accept up to 5.5V maximum V
IH). Voltage compliance on outputs (VOH) is limited by the VDDEXT supply voltage.
10Parameter value applies to USB_DP, USB_DM, and USB_VBUS pins. See Absolute Maximum Ratings on Page 40.
11Parameter value applies to all input and bidirectional pins, except PB1-0, PE15-14, PG15–11, and PH7-6.
12Parameter value applies to pins PG15–11 and PH7-6.
13Parameter value applies to pins PB1-0 and PE15-14. Consult the I2C specification version 2.1 for the proper resistor value and other open drain pin electrical parameters.
14TJ must be in the range: 0°C < TJ < 55°C during OTP memory programming operations.
Table 13. Core Clock Requirements—533 MHz and 600 MHz Speed Grade1
Parameter
Condition
Internal Regulator Setting2
Max
Unit
fCCLK
Core Clock Frequency
VDDINT = 1.30 V minimum
600
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.20 V minimum
1.25 V
533
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.14 V minimum
1.20 V
500
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.045 V minimum
1.10 V
444
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.95 V minimum
1.00 V
400
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.90 Vminimum
0.95 V
333
MHz
2 Use of an internal voltage regulator is not supported on automotive grade and 600 MHz speed grade models
Table 14. Core Clock Requirements—400 MHz Speed Grade1
Parameter
Condition
Internal Regulator Setting2
Max
Unit
fCCLK
Core Clock Frequency
VDDINT = 1.14 V minimum
1.20 V
400
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.045 V minimum
1.10 V
364
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.95 V minimum
1.00 V
333
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.90 V minimum
0.95 V
300
MHz
2 Use of an internal voltage regulator is not supported on automotive grade models
Table 15. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Maximum fCCLK
MHz
Table 16. System Clock Requirements
Parameter
Condition
DDR SDRAM Models
Mobile DDR SDRAM Models
Unit
Max
Min
Max
fSCLK
VDDINT ≥ 1.14 V
1
1332
1203
1332
MHz
fSCLK
VDDINT < 1.14 V
100
N/A4
N/A4
MHz
1 f
SCLK must be less than or equal to fCCLK.
2 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 26 on Page 43.
3 Rounded number. Actual test specification is SCLK period of 8.33 ns.
4 VDDINT must be greater than or equal to 1.14 V for mobile DDR SDRAM models. See Operating Conditions on Page 34.
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ADSP-BF561SBB500 功能描述:IC PROCESSOR 500MHZ 297PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
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