參數(shù)資料
型號： ADSP-TS101SAB2Z000
廠商： Analog Devices Inc
文件頁數(shù)： 28/48頁
文件大小： 0K
描述： IC DSP FLOAT/FIXED 250MHZ 484BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機(jī)接口，連接端口，多處理器
時鐘速率： 250MHz
非易失內(nèi)存： 外部
芯片上RAM： 768kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-BFBGA
供應(yīng)商設(shè)備封裝： 484-PBGA（19x19）
包裝： 托盤
Rev. C
|
Page 34 of 48
|
May 2009
ADSP-TS101S
TEST CONDITIONS
The test conditions for timing parameters appearing in Table 29
on Page 29 and Table 30 on Page 30 include output disable time,
output enable time, and capacitive loading. The timing specifi-
cations for the DSP apply for the voltage reference levels in
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the fol-
lowing equation:
The output disable time tDIS is the difference between
tMEASURED_DIS and tDECAY as shown in Figure 30. The time
tMEASURED_DIS is the interval from when the reference signal
switches to when the output voltage decays V from the mea-
sured output high or output low voltage. The tDECAY value is
calculated with test loads CL and IL, and with V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by V is
dependent on the capacitive load, CL, and the drive current, ID.
This ramp time can be approximated by the following equation:
The output enable time tENA is the difference between
tMEASURED_ENA and tRAMP as shown in Figure 30. The time
tMEASURED_ENA is the interval from when the reference signal
switches to when the output voltage ramps V from the mea-
sured three-stated output level. The tRAMP value is calculated
with test load CL, drive current ID, and with V equal to 0.5 V.
Capacitive Loading
Figure 31 shows the circuit with variable capacitance that is
used for measuring typical output rise and fall times. Figure 32
through Figure 39 show how output rise time varies with capac-
itance. Figure 40 graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see Output Disable Time on
Page 34.) The graphs of Figure 32 through Figure 40 may not be
linear outside the ranges shown.
Figure 29. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Figure 30. Output Enable/Disable
INPUT
OR
OUTPUT
1.5V
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V
VOL (MEASURED) + V
tMEASURED_DIS
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
OUTPUT STOPS
DRIVING
tDECAY
tENA
tMEASURED_ENA
tRAMP
t
DECAY
C
L
V
I
L
---------------
=
Figure 31. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 32. Typical Output Rise and Fall Time (10%–90%, VDD_IO =3.3 V)
vs. Load Capacitance at Strength 0
t
RAMP
C
L
V
I
D
---------------
=
1.5V
TO
OUTPUT
PIN
VARIABLE
(10pF to 100pF)
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
R
IS
E
A
N
D
F
A
L
T
IM
E
S
(n
s
)
LOAD CAPACITANCE (pF)
RISE TIME
y = 0.2015x + 3.8869
FALL TIME
y = 0.174x + 2.6931
STRENGTH 0
(VDD_IO =3.3V)
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