參數(shù)資料
型號: ADSP-TS101SAB2Z000
廠商: Analog Devices Inc
文件頁數(shù): 45/48頁
文件大小: 0K
描述: IC DSP FLOAT/FIXED 250MHZ 484BGA
標(biāo)準(zhǔn)包裝: 1
系列: TigerSHARC®
類型: 定點(diǎn)/浮點(diǎn)
接口: 主機(jī)接口,連接端口,多處理器
時(shí)鐘速率: 250MHz
非易失內(nèi)存: 外部
芯片上RAM: 768kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-BFBGA
供應(yīng)商設(shè)備封裝: 484-PBGA(19x19)
包裝: 托盤
Rev. C
|
Page 6 of 48
|
May 2009
ADSP-TS101S
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS101S processor’s external port provides the pro-
cessor’s interface to off-chip memory and peripherals. The
4G word address space is included in the DSP’s unified address
space. The separate on-chip buses—three 128-bit data buses and
three 32-bit address buses—are multiplexed at the external port
to create an external system bus with a single 64-bit data bus
and a single 32-bit address bus. The external port supports data
transfer rates of 800M bytes per second over external bus.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the
lower 32 bits of the external data bus connect to even addresses,
and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high-
order address lines to generate memory bank select signals.
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or
slow devices, host processors, and other memory-mapped
peripherals with variable access, hold, and disable time
requirements.
Figure 3. Memory Map
RESERVED
RESERV ED
INTE RNAL REG ISTERS (UREGS )
INTERNAL MEMORY 2
INTERNAL MEMORY 1
INTERNAL MEMORY 0
0x003FFFFF
0x00300000
0x00280000
0x00200000
0x001807FF
0x00180000
0x0010FFFF
0x00100000
0x0008FFFF
0x00080000
0x0000FFFF
0x00000000
INTERNAL SPACE
PROCESSOR ID 7
PROCESSOR ID 6
PROCESSOR ID 5
PROCESSOR ID 4
PROCESSOR ID 3
PROCESSOR ID 2
PROCESSOR ID 1
PROCESSOR ID 0
BROADCAST
HOST
(
MSH)
BANK 1
(
MS1)
BANK 0
(
MS0)
SDRAM
(
MSSD)
INTERNAL MEMORY
0x10000000
0x0C000000
0x08000000
0x04000000
0x03C00000
0x03800000
0x03400000
0x03000000
0x02C00000
0x02800000
0x02400000
0x02000000
0x01C00000
0x003FFFFF
0x00000000
GLOBAL SPACE
0xFFFFFFFF
M
U
L
T
IP
R
O
C
E
S
O
R
M
E
M
O
R
Y
S
P
A
C
E
X
T
E
R
N
A
L
M
E
M
O
R
Y
S
P
A
C
E
EACH IS A COPY
OF INTERNAL SPACE
RESERVED
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