參數(shù)資料
型號(hào)： ADSP-TS101SAB2Z100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CTRLR 6MBIT 300MHZ 484BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點(diǎn)/浮點(diǎn)
接口： 主機(jī)接口，連接端口，多處理器
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 768kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-BFBGA
供應(yīng)商設(shè)備封裝： 484-PBGA（19x19）
包裝： 托盤
ADSP-TS101S
Rev. C
|
Page 13 of 48
|
May 2009
Table 5. Pin Definitions—External Port Bus Controls
Signal
Type
Term
Description
ADDR31–0
1
I/O/T
nc
Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In
a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O
processor registers of other ADSP-TS101S processors. The DSP inputs addresses when a host or
another DSP accesses its internal memory or I/O processor registers.
DATA63–0
I/O/T
nc
External Data Bus. Data and instructions are received, and driven by the DSP, on these pins.
RD
2
I/O/T (pu
3)
nc
Memory Read. RD is asserted whenever the DSP reads from any slave in the system, excluding
SDRAM. When the DSP is a slave, RD is an input and indicates read transactions that access its
internal memory or universal registers. In a multiprocessor system, the bus master drives RD.
The RD pin changes concurrently with ADDR pins.
WRL2
I/O/T (pu3)nc
Write Low. WRL is asserted in two cases: When the ADSP-TS101S writes to an even address word
of external memory or to another external bus agent; and when the ADSP-TS101S writes to a
32-bit zone (host, memory, or DSP programmed to 32-bit bus). An external master (host or DSP)
asserts WRL for writing to a DSP’s low word of internal memory. In a multiprocessor system, the
bus master drives WRL. The WRL pin changes concurrently with ADDR pins. When the DSP is a
slave, WRL is an input and indicates write transactions that access its internal memory or
universal registers.
WRH2
I/O/T (pu3)nc
Write High. WRH is asserted when the ADSP-TS101S writes a long word (64 bits) or writes to an
odd address word of external memory or to another external bus agent on a 64-bit data bus.
An external master (host or another DSP) must assert WRH for writing to a DSP’s high word of
64-bit data bus. In a multiprocessing system, the bus master drives WRH. The WRH pin changes
concurrently with ADDR pins. When the DSP is a slave, WRH is an input and indicates write
transactions that access its internal memory or universal registers.
ACK
I/O/T
epu
Acknowledge. External slave devices can deassert ACK to add wait states to external memory
accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data
phase. The DSP can deassert ACK to add wait states to read accesses of its internal memory. The
ADSP-TS101S does not drive ACK during slave writes. Therefore, an external (approximately
10 k
) pull-up is required.
BMS2, 4
O/T
(pu/pd3)
au
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During reset, the
DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. When the DSP is configured to
boot from EPROM, BMS is active during the boot sequence. Pull-down enabled during RESET
(asserted); pull-up enabled after RESET (deasserted). In a multiprocessor system, the DSP bus
master drives BMS. For details see Reset and Booting on Page 9 and the EBOOT signal
description in Table 16 on Page 19.
MS1–0
O/T (pu
3)nc
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0 or 1,
respectively. MS1–0 are decoded memory address pins that change concurrently with ADDR
pins. When ADDR31:26 = 0b000010, MS0 is asserted. When ADDR31:26 = 0b000011, MS1 is
asserted. In multiprocessor systems, the master DSP drives MS1–0.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
相關(guān)PDF資料
PDF描述
TPSC156K020H0400 CAP TANT 15UF 20V 10% 2312
172-E09-202R001 CONN DB9 FEMALE SOLDER CUP TIN
VE-2WT-CY-F3 CONVERTER MOD DC/DC 6.5V 50W
172-E15-103R911 CONN DB15 MALE SOLDER CUP NICKEL
AD7818ARM-REEL IC ADC 10BIT W/TEMP SNSR 8-MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-TS201SABP-050 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-TS201SABP-060 功能描述:IC PROCESSOR 600MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-TS201SABP-10X 制造商:Analog Devices 功能描述:
ADSP-TS201SABP-15X 制造商:Analog Devices 功能描述:
ADSP-TS201SABP-ENG 制造商:Analog Devices 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*