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參數(shù)資料
| 型號(hào)： | ADV7180KST48Z |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/116頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VID DECOD SDTV 10BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 數(shù)碼相機(jī)，手機(jī)，便攜式視頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
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Data Sheet
ADV7180
Rev. I | Page 107 of 116
PCB LAYOUT RECOMMENDATIONS
The ADV7180 is a high precision, high speed, mixed-signal
device. To achieve the maximum performance from the part, it
is important to have a well laid out PCB. The following is a
guide for designing a board using the ADV7180.
ANALOG INTERFACE INPUTS
Take care when routing the inputs on the PCB. Keep track
lengths to a minimum, and use 75 trace impedances when
possible. In addition, trace impedances other than 75
increase the chance of reflections.
POWER SUPPLY DECOUPLING
It is recommended to decouple each power supply pin with
0.1 F and 10 nF capacitors. The fundamental idea is to have a
decoupling capacitor within about 0.5 cm of each power pin. In
addition, avoid placing the capacitor on the opposite side of the
PCB from the ADV7180 because doing so interposes inductive
vias in the path. The decoupling capacitors must be located
between the power plane and the power pin. Current must flow
from the power plane to the capacitor and then to the power
pin. Do not apply the power connection between the capacitor
and the power pin. Placing a via underneath the 100 nF
capacitor pads, down to the power plane, is the best approach
05700-
046
SUPPLY
GROUND
10nF
100nF
VIA TO SUPPLY
VIA TO GND
Figure 56. Recommended Power Supply Decoupling
It is particularly important to maintain low noise and good
stability of PVDD. Careful attention must be paid to regulation,
filtering, and decoupling. It is highly desirable to provide separate
regulated supplies for each of the analog circuitry groups (AVDD,
DVDD, DVDDIO, and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
analog supply voltage. This can be mitigated by regulating the
analog supply, or at least PVDD, from a different, cleaner power
source, for example, from a 12 V supply.
Using a single ground plane for the entire board is also recom-
mended.
Experience repeatedly shows that the noise performance is the
same or better with a single ground plane. Using multiple ground
planes can be detrimental because each separate ground plane is
smaller, and long ground loops can result.
PLL
Place the PLL loop filter components as close as possible to the
ELPF pin. It must also be placed on the same side of the PCB as
the ADV7180. Do not place any digital or other high frequency
traces near these components. Use the values suggested in this
data sheet with tolerances of 10% or less.
VREFN AND VREFP
Place the circuit associated with these pins as close as possible
and on the same side of the PCB as the ADV7180.
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, requiring more
current and, in turn, causing more internal digital noise.
Shorter traces reduce the possibility of reflections.
Adding a 30 to 50 series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7180.
If series resistors are used, place them as close as possible to the
ADV7180 pins. However, try not to add vias or extra length to
the output trace to place the resistors closer.
If possible, limit the capacitance that each of the digital outputs
drives to less than 15 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the ADV7180, creating more digital
noise on its power supplies.
The 40-lead and 32-lead LFCSP have an exposed metal paddle
on the bottom of the package. This paddle must be soldered to
PCB ground for proper heat dissipation and for noise and
mechanical strength benefits.
DIGITAL INPUTS
The digital inputs on the ADV7180 are designed to work with
1.8 V to 3.3 V signals and are not tolerant of 5 V signals. Extra
components are needed if 5 V logic signals are required to be
applied to the decoder.
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