參數(shù)資料
型號： ADV7180KST48Z
廠商： Analog Devices Inc
文件頁數(shù)： 8/116頁
文件大?。?/td> 0K
描述： IC VID DECOD SDTV 10BIT 48LQFP
標準包裝： 1
類型： 視頻解碼器
應用： 數(shù)碼相機，手機，便攜式視頻
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 托盤
Data Sheet
ADV7180
Rev. I | Page 105 of 116
Interrupt and VDP Map
Bit
(Shading Indicates
Default State)
Address Register
Bit Description
7 6 5 4 3 2 1 0
Comments
Notes
0x74
VDP_LINE_01E
VBI_DATA_P334_N282[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 334 (PAL), Line 282 (NTSC)
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
VBI_DATA_P21_N19[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 21 (PAL), Line 19 (NTSC)
0x75
VDP_LINE_01F
VBI_DATA_P335_N283[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 335 (PAL), Line 283 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to
be effective
VBI_DATA_P22_N20[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 22 (PAL), Line 20 (NTSC)
0x76
VDP_LINE_020
VBI_DATA_P336_N284[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 336 (PAL), Line 284 (NTSC)
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
VBI_DATA_P23_N21[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 23 (PAL), Line 21 (NTSC)
0x77
VDP_LINE_021
VBI_DATA_P337_N285[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 337 (PAL), Line 285 (NTSC)
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
VBI_DATA_P24_N22[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 24 (PAL), Line 22 (NTSC)
0x78
VDP_STATUS
(read only)
CC_AVL
0
Closed captioning not detected
CC_CLEAR resets the
CC_AVL bit
1
Closed captioning detected
CC_EVEN_FIELD
0
Closed captioning decoded from
odd field
1
Closed captioning decoded from
even field
CGMS_WSS_AVL
0
CGMS/WSS not detected
CGMS_WSS_CLEAR resets
the CGMS_WSS_AVL bit
1
CGMS/WSS detected
Reserved
0
GS_PDC_VPS_UTC_AVL
0
GS/PDC/VPS/UTC not detected
GS_PDC_VPS_UTC_CLEAR
resets the
GS_PDC_VPS_UTC_AVL
bit
1
GS/PDC/VPS/UTC detected
GS_DATA_TYPE
0
Gemstar_1× detected
1
Gemstar_2× detected
VITC_AVL
0
VITC not detected
VITC_CLEAR resets the
VITC_AVL bit
1
VITC detected
TTXT_AVL
0
Teletext not detected
1
Teletext detected
VDP_STATUS_CLEAR
(write only)
CC_CLEAR
0
Does not reinitialize the CCAP readback
registers
This is a self-clearing bit
1
Reinitializes the CCAP readback registers
Reserved
0
CGMS_WSS_CLEAR
0
Does not reinitialize the CGMS/WSS
readback registers
This is a self-clearing bit
1
Reinitializes the CGMS/WSS readback
registers
Reserved
0
GS_PDC_VPS_UTC_CLEAR
0
Does not reinitialize the GS/PDC/VPS/
UTC readback registers
This is a self-clearing bit
1
Refreshes the GS/PDC/VPS/UTC
readback registers
Reserved
0
VITC_CLEAR
0
Does not reinitialize the VITC readback
registers
This is a self-clearing bit
1
Reinitializes the VITC readback registers
Reserved
0
0x79
VDP_CCAP_DATA_0
(read only)
CCAP_BYTE_1[7:0]
x x x x x x x x
Decoded Byte 1 of CCAP
0x7A
VDP_CCAP_DATA_1
(read only)
CCAP_BYTE_2[7:0]
x x x x x x x x
Decoded Byte 2 of CCAP
0x7D
VDP_CGMS_WSS_DATA_0
(read only)
CGMS_CRC[5:2]
x x x x
Decoded CRC sequence for CGMS
Reserved
0 0 0 0
0x7E
VDP_CGMS_WSS_DATA_1
(read only)
CGMS_WSS[13:8]
x x x x x x
Decoded CGMS/WSS data
CGMS_CRC[1:0]
x x
Decoded CRC sequence for CGMS
0x7F
VDP_CGMS_WSS_DATA_2
(read only)
CGMS_WSS[7:0]
x x x x x x x x
Decoded CGMS/WSS data
0x84
VDP_GS_VPS_PDC_UTC_0
(read only)
GS_VPS_PDC_UTC_BYTE_0[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
0x85
VDP_GS_VPS_PDC_UTC_1
(read only)
GS_VPS_PDC_UTC_BYTE_1[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
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