參數(shù)資料
型號(hào): ADV7189BKSTZ
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 91/104頁(yè)
文件大?。?/td> 0K
描述: IC DECODER VIDEO W/ADC 80LQFP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 視頻解碼器
應(yīng)用: 機(jī)頂盒,視頻播放器,錄音機(jī)
電壓 - 電源,模擬: 3.15 V ~ 3.45 V
電壓 - 電源,數(shù)字: 1.65 V ~ 2 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 788 (CN2011-ZH PDF)
ADV7189B
Rev. B | Page 87 of 104
Bits
Subaddress
Register
Bit Description
7
6
5
4
3
2
1
0
Comments
Notes
NVBEG[4:0]. How many lines after
lCOUNT rollover to set V high.
0
1
0
1
NTSC default (BT.656)
0
Set to low when manual
programming
NVBEGSIGN
1
Not suitable for user
programming
0
No delay
NVBEGDELE. Delay V bit going
high by one line relative to
NVBEG (even field).
1
Additional delay by
1 line
0
No delay
0xE5
NTSC V Bit
Begin
NVBEGDELO. Delay V bit going
high by one line relative to
NVBEG (odd field).
1
Additional delay by
1 line
NVEND[4:0]. How many lines
after lCOUNT rollover to set V low.
0
1
0
NTSC default (BT.656)
0
Set to low when manual
programming
NVENDSIGN
1
Not suitable for user
programming
0
No delay
NVENDDELE. Delay V bit going
low by one line relative to NVEND
(even field).
1
Additional delay by
1 line
0
No delay
0xE6
NTSC V Bit
End
NVENDDELO. Delay V bit going
low by one line relative to NVEND
(odd field).
1
Additional delay by
1 line
NFTOG[4:0]. How many lines after
lCOUNT rollover to toggle F signal.
0
1
NTSC default
0
Set to low when manual
programming
NFTOGSIGN
1
Not suitable for user
programming
0
No delay
NFTOGDELE. Delay F transition
by one line relative to NFTOG
(even field).
1
Additional delay by
1 line
0
No delay
0xE7
NTSC F Bit
Toggle
NFTOGDELO. Delay F transition
by one line relative to NFTOG
(odd field).
1
Additional delay by
1 line
PVBEG[4:0]. How many lines after
lCOUNT rollover to set V high.
0
1
0
1
PAL default (BT.656)
0
Set to low when manual
programming
PVBEGSIGN
1
Not suitable for user
programming
0
No delay
PVBEGDELE. Delay V bit going
high by one line relative to
PVBEG (even field).
1
Additional delay by
1 line
0
No delay
0xE8
PAL V Bit
Begin
PVBEGDELO. Delay V bit going
high by one line relative to
PVBEG (odd field).
1
Additional delay by
1 line
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