- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294984 > AGLP125V5CSG281I FPGA, 3120 CLBS, 125000 GATES, PBGA281 PDF資料下載
參數(shù)資料
| 型號(hào)： | AGLP125V5CSG281I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 3120 CLBS, 125000 GATES, PBGA281 |
| 封裝： | 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, ROHS COMPLIANT, CSP-281 |
| 文件頁(yè)數(shù)： | 24/128頁(yè) |
| 文件大小： | 4383K |
| 代理商： | AGLP125V5CSG281I |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
IGLOO PLUS Device Family Overview
1- 6
R ev isio n 1 1
SRAM and FIFO
IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side.
Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are
256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports
that can be configured with different bit widths on each port. For example, data can be sent through a
4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device
JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC) capabilities.
Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL.
The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine
access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time is 300 s (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases (for PLL only) is 40 ps ×
250 MHz / fOUT_CCC
Global Clocking
IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGLP125V5CSG281 | FPGA, 3120 CLBS, 125000 GATES, PBGA281 |
| AGLP125V5CSG289I | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| AGLP125V5CSG289 | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| AGLP060V2-CS201I | FPGA, 1584 CLBS, 60000 GATES, PBGA201 |
| AGLP060V2-CS201 | FPGA, 1584 CLBS, 60000 GATES, PBGA201 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLP125V5-CSG281I | 功能描述:IC FPGA IGLOO PLUS 125K 281-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| AGLP125-V5CSG289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V5-CSG289 | 功能描述:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| AGLP125-V5CSG289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125-V5CSG289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。