參數(shù)資料
型號: AGLP125V5CSG281I
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA281
封裝: 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, ROHS COMPLIANT, CSP-281
文件頁數(shù): 70/128頁
文件大小: 4383K
代理商: AGLP125V5CSG281I
IGLOO PLUS DC and Switching Characteristics
2- 32
R e v i sio n 1 1
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-46 Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
1
IIH
2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
–0.3
0.7
1.7
3.6
0.7
1.7
2
16
18
10
4 mA
–0.3
0.7
1.7
3.6
0.7
1.7
4
16
18
10
6 mA
–0.3
0.7
1.7
3.6
0.7
1.7
6
32
37
10
8 mA
–0.3
0.7
1.7
3.6
0.7
1.7
8
32
37
10
12 mA
–0.3
0.7
1.7
3.6
0.7
1.7
12
65
74
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-8
AC Loading
Table 2-47 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
02.5
1.2
5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
5 pF for tHZ / tLZ
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