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參數(shù)資料
| 型號： | AGLP125V5CSG281I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 3120 CLBS, 125000 GATES, PBGA281 |
| 封裝： | 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, ROHS COMPLIANT, CSP-281 |
| 文件頁數(shù)： | 99/128頁 |
| 文件大小： | 4383K |
| 代理商： | AGLP125V5CSG281I |
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IGLOO PLUS DC and Switching Characteristics
2- 58
R e v i sio n 1 1
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-61. Table 2-84 to Table 2-89 on page 2-60 present
minimum and maximum global clock delays within each device. Minimum and maximum delays are
measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-84 AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.21
1.42
ns
tRCKH
Input High Delay for Global Clock
1.23
1.49
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.27
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-85 AGLP060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.32
1.62
ns
tRCKH
Input High Delay for Global Clock
1.34
1.72
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.38
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLP125V5-CSG281I | 功能描述:IC FPGA IGLOO PLUS 125K 281-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| AGLP125-V5CSG289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V5-CSG289 | 功能描述:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| AGLP125-V5CSG289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125-V5CSG289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
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