參數(shù)資料
型號(hào): AGLP125V5CSG281I
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA281
封裝: 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, ROHS COMPLIANT, CSP-281
文件頁數(shù): 50/128頁
文件大?。?/td> 4383K
代理商: AGLP125V5CSG281I
IGLOO PLUS DC and Switching Characteristics
2- 14
R e v i sio n 1 1
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
The average toggle rate of an 8-bit counter is 25%:
Bit 0 (LSB) = 100%
Bit 1
= 50%
Bit 2
= 25%
–…
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
Table 2-19 Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
α
1
Toggle rate of VersaTile outputs
10%
α
2
I/O buffer toggle rate
10%
Table 2-20 Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
Guideline
β
1
I/O output buffer enable rate
100%
β
2
RAM enable rate for read operations
12.5%
β
3
RAM enable rate for write operations
12.5%
相關(guān)PDF資料
PDF描述
AGLP125V5CSG281 FPGA, 3120 CLBS, 125000 GATES, PBGA281
AGLP125V5CSG289I FPGA, 3120 CLBS, 125000 GATES, PBGA289
AGLP125V5CSG289 FPGA, 3120 CLBS, 125000 GATES, PBGA289
AGLP060V2-CS201I FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CS201 FPGA, 1584 CLBS, 60000 GATES, PBGA201
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