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參數(shù)資料
| 型號： | AM29LV320DB120 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 32兆位（4個M × 8位/ 2米x 16位），3.0伏的CMOS只，引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 11/55頁 |
| 文件大小： | 1258K |
| 代理商： | AM29LV320DB120 |
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November 15, 2004
Am29LV320D
11
DEVICE BUS OPERATIONS
This section describes the requirements and
use of the device bus operations, which are ini-
tiated through the internal command register.
The command register itself does not occupy
any addressable memory location. The register
is a latch used to store the commands, along
with the address and data information needed
to execute the command. The contents of the
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function of the device.
Table 1
lists the device
bus operations, the inputs and control levels
they require, and the resulting output. The fol-
lowing subsections describe each of these oper-
ations in further detail.
Table 1.
Am29LV320D Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V, V
HH
= 11.5–12.5 V, X = Don’t Care, SA
= Sector Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A20:A0 in word mode (BYTE# = V
IH
), A20:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
“Sector/Sector Block Protection and Unprotection” on page 17
.
3. If WP#/ACC = V
IL
, the two outermost boot sectors remain protected. If WP#/ACC = V
IH
, the two outermost boot
sector protection depends on whether they were last protected or unprotected using the method described in
“Sector/Sector Block Protection and Unprotection” on page 17
. If WP#/ACC = V
HH
, all sectors are unprotected.
4. D
IN
or D
OUT
as required by command sequence, data polling, or sector protection algorithm.
Word/Byte Configuration
The BYTE# pin controls whether the device
data I/O pins operate in the byte or word con-
figuration. If the BYTE# pin is set at logic ‘1’,
the device is in word configuration, DQ0–DQ15
are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is
in byte configuration, and only data I/O pins
DQ0–DQ7 are active and controlled by CE# and
OE#. The data I/O pins DQ8–DQ14 are
tri-stated, and the DQ15 pin is used as an input
for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the sys-
tem must drive the CE# and OE# pins to V
IL
.
CE# is the power control and selects the de-
vice. OE# is the output control and gates array
data to the output pins. WE# should remain at
V
IH
. The BYTE# pin determines whether the de-
vice outputs array data in words or bytes.
Operation
CE#
OE#
WE
#
RESET
#
WP#/AC
C
Addresses
(Note 2)
DQ0–
DQ7
DQ8–DQ15
BYTE
#
= V
IH
BYTE#
= V
IL
Read
L
L
H
H
L/H
A
IN
D
OUT
D
OUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write
L
H
L
H
(Note 3)
A
IN
(Note 4) (Note 4)
Accelerated Program
L
H
L
H
V
HH
A
IN
(Note 4) (Note 4)
Standby
V
±
0.3 V
X
X
V
±
0.3 V
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
L/H
X
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
L/H
SA, A6 = L,
A1 = H, A0 = L
(Note 4)
X
X
Sector Unprotect
(Note 2)
L
H
L
V
ID
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
(Note 4)
X
X
Temporary Sector
Unprotect
X
X
X
V
ID
(Note 3)
A
IN
(Note 4) (Note 4)
High-Z
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM29LV320DB120EI | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 120ns 48-Pin TSOP |
| AM29LV320DB120WMI | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 120ns 48-Pin FBGA |
| AM29LV320DB90EC | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP |
| AM29LV320DB90ED | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP |
| AM29LV320DB90EF | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 4M x 8/2M x 16 90ns 48-Pin TSOP |
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